Hello, We are team from Jordan University of Science and Technology - this final project in JoSDC'23 (Jordan national Semiconductors Design Competition )
The pipeline CPU implemented here is designed to execute a subset of the MIPS instruction set. It fetches and executes one instruction every clock cycle, making it a straightforward design for educational purposes.
Modules/: Contains the Verilog source files for the CPU and its components.
this our modules in code :
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