iss-testing: Add Zicsr trap test

Author: Jozott00

vadl/main/vadl/ast/BehaviorLowering.java

@@ -335,6 +335,8 @@ private ExpressionNode fetch(Expr expr) {
     var result = expr.accept(this);
     result.setSourceLocationIfNotSet(expr.location());
     expressionCache.put(expr, result);
+    result.ensure(!(result.type() instanceof ConstantType),
+        "Constant types must not exist in the VIAM");
     return result;
   }
 

vadl/test/vadl/iss/AsmTestBuilder.java

@@ -61,8 +61,9 @@ public BigInteger fillReg(String reg, int size) {
     );
   }
 
-  public void addLabel(String label) {
+  public AsmTestBuilder addLabel(String label) {
     add("%s:", label);
+    return this;
   }
 
   @FormatMethod

vadl/test/vadl/iss/IssInstrTest.java

@@ -21,6 +21,7 @@
 
 import java.io.IOException;
 import java.util.Collection;
+import java.util.Comparator;
 import java.util.List;
 import java.util.Map;
 import java.util.function.Function;
@@ -61,6 +62,12 @@ public Map<String, String> toMap() {
 
   public abstract Tool compiler();
 
+
+  protected final Stream<DynamicTest> runTest(
+      IssTestUtils.TestCase test) throws IOException {
+    return runTestsWith(1, (i) -> test);
+  }
+
   @SafeVarargs
   protected final Stream<DynamicTest> runTestsWith(
       Function<Integer, IssTestUtils.TestCase>... generators) throws IOException {
@@ -148,7 +155,13 @@ protected Stream<DynamicTest> runQemuInstrTests(ImageFromDockerfile image,
               System.out.println("Test " + e.id());
               System.out.println("ASM: \n" + testSpec.asmCore());
               System.out.println("\nRan stages: " + e.completedStages());
-              System.out.println("Register tests: \n" + e.regTests());
+              System.out.println("Register tests: ");
+              e.regTests().stream()
+                  .sorted(Comparator.comparing(IssTestUtils.TestResult.RegTestResult::reg))
+                  .forEachOrdered(r -> {
+                    System.out.println(
+                        "- " + r.reg() + " exp: " + r.expected() + " act: " + r.actual());
+                  });
               System.out.println("Duration: " + e.duration());
 
               if (!success) {

vadl/test/vadl/iss/QemuIssTest.java

@@ -18,12 +18,13 @@
 
 import java.io.IOException;
 import java.nio.file.Path;
+import java.util.Arrays;
 import java.util.Map;
 import java.util.concurrent.ConcurrentHashMap;
+import java.util.stream.Collectors;
 import org.slf4j.Logger;
 import org.slf4j.LoggerFactory;
 import org.testcontainers.images.builder.ImageFromDockerfile;
-import org.testcontainers.shaded.org.checkerframework.checker.nullness.qual.Nullable;
 import vadl.DockerExecutionTest;
 import vadl.configuration.IssConfiguration;
 import vadl.pass.PassOrders;
@@ -90,7 +91,7 @@ private ImageFromDockerfile generateSimulator(Map<String, ImageFromDockerfile> c
         }
 
         // generate iss image from the output path
-        return getIssImage(issOutputPath, configuration, "riscv64-softmmu");
+        return getIssImage(issOutputPath, configuration, "riscv64-softmmu", "riscv32-softmmu");
       } catch (IOException | DuplicatedPassKeyException e) {
         throw new RuntimeException(e);
       }
@@ -102,13 +103,13 @@ private ImageFromDockerfile generateSimulator(Map<String, ImageFromDockerfile> c
    * This will produce a new image for the given generated iss sources.
    *
    * @param generatedIssSources the path to the generated ISS/QEMU sources.
-   * @param referenceTarget     The reference target that should also be compiled
+   * @param referenceTargets    The reference targets that should also be build
    *                            (e.g. riscv64-softmmu)
    * @return a new image that builds the ISS at build time.
    */
   private ImageFromDockerfile getIssImage(Path generatedIssSources,
                                           IssConfiguration configuration,
-                                          @Nullable String referenceTarget
+                                          String... referenceTargets
   ) {
 
     // get redis cache for faster compilation using sccache
@@ -117,7 +118,8 @@ private ImageFromDockerfile getIssImage(Path generatedIssSources,
     var targetName = configuration.targetName().toLowerCase();
     var softmmuTarget = targetName + "-softmmu";
     var qemuBin = "qemu-system-" + targetName;
-    var refTarget = referenceTarget == null ? "" : "," + referenceTarget;
+    var refTargetString = Arrays.stream(referenceTargets).collect(Collectors.joining(","));
+    var refTarget = refTargetString.isEmpty() ? "" : "," + refTargetString;
 
     var dockerImage = new ImageFromDockerfile()
         .withDockerfileFromBuilder(d -> {

vadl/test/vadl/iss/riscv/AbstractIssRiscv32InstrTest.java

@@ -0,0 +1,45 @@
+// SPDX-FileCopyrightText : © 2025 TU Wien <[email protected]>
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+package vadl.iss.riscv;
+
+import java.util.Map;
+import vadl.iss.IssInstrTest;
+
+public abstract class AbstractIssRiscv32InstrTest extends IssInstrTest {
+
+
+  @Override
+  public Map<String, String> gdbRegMap() {
+    return AbstractIssRiscv64InstrTest.GDB_REF_MAP;
+  }
+
+  @Override
+  public Tool simulator() {
+    return new Tool("/qemu/build/qemu-system-rv32zicsr", "-bios");
+  }
+
+  @Override
+  public Tool reference() {
+    return new Tool("/qemu/build/qemu-system-riscv32", "-M spike -bios");
+  }
+
+  @Override
+  public Tool compiler() {
+    return new Tool("/scripts/compilers/riscv_compiler.py", "-march=rv32imzicsr -mabi=ilp32");
+  }
+
+}

vadl/test/vadl/iss/riscv/IssRV32ZicsrInstrTest.java

@@ -0,0 +1,74 @@
+// SPDX-FileCopyrightText : © 2025 TU Wien <[email protected]>
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+package vadl.iss.riscv;
+
+import java.io.IOException;
+import java.util.stream.Stream;
+import org.junit.jupiter.api.DynamicTest;
+import org.junit.jupiter.api.TestFactory;
+import vadl.iss.AsmTestBuilder;
+import vadl.iss.IssTestUtils;
+
+public class IssRV32ZicsrInstrTest extends AbstractIssRiscv32InstrTest {
+  private static final String VADL_SPEC = "sys/risc-v/rv32csr.vadl";
+  private static final int TESTS_PER_INSTRUCTION = 50;
+
+  @Override
+  public int getTestPerInstruction() {
+    return TESTS_PER_INSTRUCTION;
+  }
+
+  @Override
+  public String getVadlSpec() {
+    return VADL_SPEC;
+  }
+
+  @Override
+  public AsmTestBuilder getBuilder(String testNamePrefix, int id) {
+    return new RV64IMTestBuilder(testNamePrefix + "_" + id);
+  }
+
+  @TestFactory
+  Stream<DynamicTest> testSimpleTrap() throws IOException {
+    var asmCore = """
+        la t0, handler
+        csrw mtvec, t0
+        
+        li a2, 1
+        li a0, 1
+        li a1, 1
+        ebreak
+        li a0, 2
+        j exit
+        
+        handler:
+        csrr t1, mepc
+        addi t1, t1, 4
+        csrw mepc, t1
+        addi t2, x0, 5
+        csrr a3, mcause
+        mret
+        
+        li a2, 2 # should not reach this 
+        
+        exit:
+        """;
+    return runTest(new IssTestUtils.TestCase("Simple Trap", asmCore));
+  }
+
+
+}