iss: Initial support and testing of current AArch64 implementation

sys/aarch64/aarch64.vadl

@@ -184,7 +184,7 @@ instruction set architecture AArch64Base = {
   // register shift expression, encoding elements, assembly string expression
   record RegShift (ex: Ex, enc: Encs, asm: Ex)
 
-  // register size (WSize, XSize), access size (Byte, Half, Word, XWord), 
+  // register size (WSize, XSize), access size (Byte, Half, Word, XWord),
   // mnemonic extension ("b", "sb", "h", "sh", "sw"), opc, memory statement
   record Memory  (regsize: Id, accsize: Id, mext: Str, opc: Lit, stmt: Stat)
 
@@ -271,7 +271,7 @@ instruction set architecture AArch64Base = {
         }
     //[raise Undefined : imm3(2) = 1 && imm3(1..0) != 0]
     encoding ExtendId ($i.id, $extId) = { op = $i.opcode, sf = SF::$size, ff = FF::$f.ff, option = ExtendType::$optId, $enc }
-    assembly ExtendId ($i.id, $extId) = ( $i.mnemo, $f.mext, ' ', ExtendId($size, match: Str ($f.ff = OffFlags => "SP" ; _ => ""))(rd), 
+    assembly ExtendId ($i.id, $extId) = ( $i.mnemo, $f.mext, ' ', ExtendId($size, match: Str ($f.ff = OffFlags => "SP" ; _ => ""))(rd),
                        ', ', ExtendId($size, "SP")(rn), ', ', $asm )
     }
 
@@ -777,7 +777,7 @@ instruction set architecture AArch64Base = {
 
 // reverse bits / bytes model **************************************************
 
-  function revBitsWSize (bits: BitsW) -> BitsW = bits 
+  function revBitsWSize (bits: BitsW) -> BitsW = bits
     ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,
      16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31)
 

vadl-cli/main/vadl/cli/BaseCommand.java

@@ -16,6 +16,7 @@
 
 package vadl.cli;
 
+import static org.apache.commons.lang3.exception.ExceptionUtils.getStackTrace;
 import static picocli.CommandLine.ScopeType.INHERIT;
 
 import com.google.errorprone.annotations.concurrent.LazyInit;
@@ -86,6 +87,12 @@ public abstract class BaseCommand implements Callable<Integer> {
       description = "Expand all macros and write them to disk.")
   boolean expandMacros;
 
+  @Option(names = "--with-stacktrace",
+      scope = INHERIT,
+      description = "Debug option to show the OpenVADL stacktrace of an emitted error."
+  )
+  boolean showStacktrace;
+
   /**
    * A list of timings. Will only be filled when the timings should be recorded.
    */
@@ -308,9 +315,15 @@ public Integer call() {
 
     } catch (Diagnostic d) {
       System.out.println(new DiagnosticPrinter().toString(d));
+      if (showStacktrace) {
+        System.out.println(getStackTrace(d));
+      }
       returnVal = 1;
     } catch (DiagnosticList d) {
       System.out.println(new DiagnosticPrinter().toString(d));
+      if (showStacktrace) {
+        System.out.println(getStackTrace(d));
+      }
       returnVal = 1;
     } catch (RuntimeException | IOException | DuplicatedPassKeyException e) {
       System.out.println("""

vadl/main/resources/templates/common/vadl-builtins.h

@@ -19,6 +19,7 @@
 
 #include <assert.h>
 #include <stdint.h>
+#include <stdarg.h>
 
 typedef uint64_t Bits; // Generic 64-bit container of bit patterns
 typedef Bits UInt; // Interpreted as an unsigned 64-bit integer
@@ -699,4 +700,67 @@ static inline Bits VADL_cls(Bits a, Width w) {
 }
 
 
+/************************
+ * MISC
+ ************************/
+
+/*-----------------------------------------------------------------------
+ *    concat(a: Bits<N>, b: Bits<M>) -> Bits<N + M> (concatenate bits)
+ *---------------------------------------------------------------------*/
+static inline Bits VADL_concat(Bits a, Width aw, Bits b, Width bw) {
+  Width res_w = aw + bw;
+  a = VADL_uextract(a, aw);
+  b = VADL_uextract(b, bw);
+  // shift a << b.width
+  Bits shifted = VADL_lsl(a, aw, bw, 32);
+  return VADL_or(shifted, res_w, b, res_w);
+}
+
+/**
+ * Extracts and concatenates specified bit ranges from a 64-bit value.
+ *
+ * @param v      The 64-bit input value.
+ * @param nparts The number of (hi, lo) index pairs provided.
+ * @param ...    A variable list of integer pairs: hi1, lo1, hi2, lo2, ..., hin, lon.
+ *               Each pair defines a bit range from bit lo to bit hi (inclusive).
+ *               Bits are extracted and concatenated in the order provided,
+ *               starting from the least significant bit of the result.
+ *
+ * @return A 64-bit value containing the concatenated bits from the specified ranges.
+ *
+ * Example:
+ *   VADL_slice(0xF0F0, 2, 11, 8, 3, 0)
+ *   Extracts bits 11..8 and 3..0 from 0xF0F0 and concatenates them into the result.
+ */
+static inline Bits VADL_slice(uint64_t v, uint32_t nparts, ...) {
+    va_list ap;
+    va_start(ap, nparts);
+
+    va_list ap2;
+    va_copy(ap2, ap);
+    uint32_t total_width = 0;
+    for (uint32_t i = 0; i < nparts; ++i) {
+        int hi = va_arg(ap2, int);
+        int lo = va_arg(ap2, int);
+        total_width += (hi - lo + 1);
+    }
+    va_end(ap2);
+
+    uint64_t result = 0;
+    uint32_t out_bit = total_width;
+
+    for (uint32_t i = 0; i < nparts; ++i) {
+        int hi = va_arg(ap, int);
+        int lo = va_arg(ap, int);
+        int width = hi - lo + 1;
+        out_bit -= width;
+        uint64_t mask = VADL_mask(width);
+        uint64_t part = (v >> lo) & mask;
+        result |= (part << out_bit);
+    }
+
+    va_end(ap);
+    return result;
+}
+
 #endif //VADL_BUILTINS_H

vadl/main/resources/templates/htmlDump/index.html

@@ -98,7 +98,7 @@ <h2 id="passes-heading">
 
         <h4 class="text-md font-semibold tracking-wide text-gray-900">[[${number}]]</h4>
         <div>
-            <h4 class="text-md font-semibold tracking-wide text-gray-900">[[${singlePass.pass.name}]] ([[${singlePass.durationMs}]] ms)</h4>
+            <h4 class="text-md font-semibold tracking-wide text-gray-900">[[${singlePass.pass.name}]] ([[${singlePass.duration}]] ms)</h4>
             <div class="inline-grid items-center gap-2" style="grid-template-columns: auto auto;">
                 <span class="text-gray-500 font-medium text-sm">Key</span>
                 <span class="badge text-blue-800 text-sm">[[${singlePass.passKey}]]</span>

vadl/main/vadl/ast/TypeChecker.java

@@ -1706,6 +1706,7 @@ public Void visit(SpecialPurposeRegisterDefinition definition) {
   @Override
   public Void visit(ProcessorDefinition definition) {
     definition.definitions.forEach(this::check);
+    check(definition.implementedIsaNode());
 
     // FIXME: Do we need to limit certain operations here?
     //  (like Resource access -- except memory write of course)

vadl/main/vadl/ast/ViamLowering.java

@@ -893,7 +893,8 @@ private <T extends Definition & IdentifiableNode> Function produceFunction(
       parameterCache.put(parameter, viamParameter);
       parameters.add(viamParameter);
     }
-    var behavior = new BehaviorLowering(this).getFunctionGraph(expr, "behaviour");
+    var behavior =
+        new BehaviorLowering(this).getFunctionGraph(expr, identifier.simpleName() + " behavior");
 
     return new Function(identifier,
         parameters.toArray(new vadl.viam.Parameter[0]),

vadl/main/vadl/cppCodeGen/CppTypeMap.java

@@ -150,4 +150,29 @@ private static int nextFittingBitSize(int old) {
 
     throw new RuntimeException("Types with more than 128 bits are not supported");
   }
+
+  /**
+   * Returns the next fitting unsigned integer as C stdint string.
+   * This will only look at the bit-width of the type.
+   * It assumes that the given type is a {@link vadl.types.DataType}.
+   */
+  public static String nextFittingUInt(Type type) {
+    return nextFittingUInt(type.asDataType().bitWidth());
+  }
+
+  /**
+   * Returns the next fitting unsigned integer as C stdint string.
+   */
+  public static String nextFittingUInt(int size) {
+    if (size <= 8) {
+      return "uint8_t";
+    } else if (size <= 16) {
+      return "uint16_t";
+    } else if (size <= 32) {
+      return "uint32_t";
+    } else if (size <= 64) {
+      return "uint64_t";
+    }
+    throw new RuntimeException("Types with more than 64 bits are not supported");
+  }
 }

vadl/main/vadl/cppCodeGen/FunctionCodeGenerator.java

@@ -34,7 +34,6 @@
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadMemNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
-import vadl.viam.graph.dependency.SliceNode;
 
 /**
  * Abstract base class responsible for generating C code from a given function's expression nodes.
@@ -82,10 +81,6 @@ public FunctionCodeGenerator(Function function) {
   @Handler
   protected abstract void handle(CGenContext<Node> ctx, AsmBuiltInCall toHandle);
 
-  @Override
-  @Handler
-  public abstract void handle(CGenContext<Node> ctx, SliceNode toHandle);
-
   public String genReturnExpression() {
     var returnNode = getSingleNode(function.behavior(), ReturnNode.class);
     return context.genToString(returnNode.value());

vadl/main/vadl/cppCodeGen/common/AccessFunctionCodeGenerator.java

@@ -36,7 +36,6 @@
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadMemNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
-import vadl.viam.graph.dependency.SliceNode;
 
 /**
  * Produce a pure function that allows to access format field references.
@@ -119,11 +118,6 @@ protected void handle(CGenContext<Node> ctx, ReadArtificialResNode toHandle) {
     throwNotAllowed(toHandle, "Artificial resource reads");
   }
 
-  @Override
-  public void handle(CGenContext<Node> ctx, SliceNode toHandle) {
-    throwNotAllowed(toHandle, "Slice node reads");
-  }
-
   @Override
   public void handle(CGenContext<Node> ctx, FuncParamNode toHandle) {
     // Explicit parameters are not allowed. The only parameter is the implicit format field access.

vadl/main/vadl/cppCodeGen/common/AsmParserFunctionCodeGenerator.java

@@ -32,7 +32,6 @@
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadMemNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
-import vadl.viam.graph.dependency.SliceNode;
 
 /**
  * Produce a function that can access special functions of the asm parser.
@@ -72,10 +71,6 @@ public void handle(CGenContext<Node> ctx, FieldRefNode toHandle) {
     throwNotAllowed(toHandle, "Format field accesses");
   }
 
-  @Override
-  public void handle(CGenContext<Node> ctx, SliceNode toHandle) {
-    throwNotAllowed(toHandle, "Slice node reads");
-  }
 
   @Override
   public void handle(CGenContext<Node> ctx, ConstantNode toHandle) {

vadl/main/vadl/cppCodeGen/common/PureFunctionCodeGenerator.java

@@ -28,7 +28,6 @@
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadMemNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
-import vadl.viam.graph.dependency.SliceNode;
 
 /**
  * Produce a pure function that does not access any entities except parameters.
@@ -74,8 +73,4 @@ public void handle(CGenContext<Node> ctx, AsmBuiltInCall toHandle) {
     throwNotAllowed(toHandle, "Asm builtin calls");
   }
 
-  @Override
-  public void handle(CGenContext<Node> ctx, SliceNode toHandle) {
-    throwNotAllowed(toHandle, "Slice node reads");
-  }
 }

vadl/main/vadl/cppCodeGen/mixins/CDefaultMixins.java

@@ -331,8 +331,15 @@ default void handle(CGenContext<Node> ctx, ConstantNode constant) {
   @SuppressWarnings("MissingJavadocType")
   interface Slice {
     @Handler
-    default void handle(CGenContext<Node> ctx, SliceNode toHandle) {
-      throw new UnsupportedOperationException("Type SliceNode not yet implemented");
+    @SuppressWarnings("MissingJavadocMethodCheck")
+    default void handle(CGenContext<Node> ctx, SliceNode node) {
+      ctx.wr("VADL_slice(")
+          .gen(node.value())
+          .wr(", %s", node.bitSlice().partSize());
+      node.bitSlice().parts().forEach(p -> {
+        ctx.wr(", " + p.msb() + ", " + p.lsb());
+      });
+      ctx.wr(")");
     }
   }
 

vadl/main/vadl/iss/codegen/IssCMixins.java

@@ -16,10 +16,13 @@
 
 package vadl.iss.codegen;
 
-import static vadl.error.DiagUtils.throwNotAllowed;
-
 import vadl.cppCodeGen.context.CGenContext;
 import vadl.iss.passes.nodes.IssConstExtractNode;
+import vadl.iss.passes.nodes.IssValExtractNode;
+import vadl.iss.passes.opDecomposition.nodes.IssMul2Node;
+import vadl.iss.passes.opDecomposition.nodes.IssMulhNode;
+import vadl.iss.passes.safeResourceRead.nodes.ExprSaveNode;
+import vadl.iss.passes.tcgLowering.TcgExtend;
 import vadl.javaannotations.Handler;
 import vadl.viam.graph.Node;
 import vadl.viam.graph.dependency.WriteRegTensorNode;
@@ -31,30 +34,50 @@
  */
 public interface IssCMixins {
 
-  /**
-   * Bundles all Invalid ISS node mixins.
-   */
-  interface Invalid extends IssExpr {
-
-  }
-
   /**
    * Bundles all valid ISS node mixins.
    */
-  interface Default extends IssExtract {
+  interface Default extends IssExtract, IssExpr {
   }
 
   /**
-   * The invalid ISS Expr Node mixin.
+   * ISS specific expressions (subtypes of
+   * {@link vadl.iss.passes.opDecomposition.nodes.IssExprNode}).
    */
   interface IssExpr {
+    @Handler
+    @SuppressWarnings("MissingJavadocMethod")
+    default void handle(CGenContext<Node> ctx, IssValExtractNode node) {
+      var valW = node.value().type().asDataType().bitWidth();
+      var ofsW = node.ofs().type().asDataType().bitWidth();
+      var lenW = node.len().type().asDataType().bitWidth();
+      // we perform a shift >> to clear the offset.
+      // then we extract the result using (s/u)extract.
+
+      var extract = node.extendMode() == TcgExtend.ZERO ? "VADL_uextract" : "VADL_sextract";
+
+      ctx.wr(extract + "( ");
+      // inner shift of value
+      ctx.wr("VADL_lsr(").gen(node.value())
+          .wr(", %s, ", valW).gen(node.value()).wr(", %s)", ofsW);
+
+      ctx.wr(", %s )", lenW);
+    }
 
     @Handler
-    default void handle(CGenContext<Node> ctx,
-                        vadl.iss.passes.opDecomposition.nodes.IssExprNode node) {
-      throwNotAllowed(node, "IssExprNode");
+    default void handle(CGenContext<Node> ctx, ExprSaveNode toHandle) {
+      throw new UnsupportedOperationException("Type ExprSaveNode not yet implemented");
     }
 
+    @Handler
+    default void handle(CGenContext<Node> ctx, IssMulhNode toHandle) {
+      throw new UnsupportedOperationException("Type IssMulhNode not yet implemented");
+    }
+
+    @Handler
+    default void handle(CGenContext<Node> ctx, IssMul2Node toHandle) {
+      throw new UnsupportedOperationException("Type IssMul2Node not yet implemented");
+    }
   }
 
   /**

vadl/main/vadl/iss/codegen/IssTranslateCodeGenerator.java

@@ -25,7 +25,6 @@
 import vadl.cppCodeGen.mixins.CInvalidMixins;
 import vadl.iss.passes.nodes.IssStaticPcRegNode;
 import vadl.iss.passes.nodes.TcgVRefNode;
-import vadl.iss.passes.safeResourceRead.nodes.ExprSaveNode;
 import vadl.iss.passes.tcgLowering.nodes.TcgNode;
 import vadl.javaannotations.DispatchFor;
 import vadl.javaannotations.Handler;
@@ -50,7 +49,7 @@ public class IssTranslateCodeGenerator implements
     // default implementations
     CDefaultMixins.All, IssCMixins.Default,
     // invalid nodes
-    IssCMixins.Invalid, CInvalidMixins.SideEffect, CInvalidMixins.ResourceReads,
+    CInvalidMixins.SideEffect, CInvalidMixins.ResourceReads,
     CInvalidMixins.InstrCall, CInvalidMixins.HardwareRelated {
 
   private Instruction insn;
@@ -131,11 +130,6 @@ void impl(CGenContext<Node> ctx, FieldAccessRefNode node) {
     ctx.wr(node.fieldAccess().simpleName());
   }
 
-  @Handler
-  void handle(CGenContext<Node> ctx, ExprSaveNode toHandle) {
-    throw new UnsupportedOperationException("Type ExprSaveNode not yet implemented");
-  }
-
   @Handler
   void handle(CGenContext<Node> ctx, TcgVRefNode toHandle) {
     ctx.wr(toHandle.cCode());