clockgate: set default initialization with 0 to fix X in vcs (#3031)

Author: Maxpicca-Li

src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala

@@ -110,7 +110,7 @@ class LoadQueueRAR(implicit p: Parameters) extends XSModule
 
   // Allocate logic
   val acceptedVec = Wire(Vec(LoadPipelineWidth, Bool()))
-  val enqIndexVec = Wire(Vec(LoadPipelineWidth, UInt()))
+  val enqIndexVec = Wire(Vec(LoadPipelineWidth, UInt(log2Up(LoadQueueRARSize).W)))
 
   for ((enq, w) <- io.query.map(_.req).zipWithIndex) {
     acceptedVec(w) := false.B

src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala

@@ -118,7 +118,7 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule
 
   // Allocate logic
   val acceptedVec = Wire(Vec(LoadPipelineWidth, Bool()))
-  val enqIndexVec = Wire(Vec(LoadPipelineWidth, UInt()))
+  val enqIndexVec = Wire(Vec(LoadPipelineWidth, UInt(log2Up(LoadQueueRAWSize).W)))
 
   // Enqueue
   for ((enq, w) <- io.query.map(_.req).zipWithIndex) {