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- #4556 · NewPaulWalker opened
on Apr 14, 2025 1 - #4242 · castleberrysam opened
on Feb 2, 2025 11
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A misaligned store that crosses a page in VS-mode hangs the core when the second page takes a guest-page fault
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6632 In OpenXiangShan/XiangShan;M-mode strided and indexed vector accesses are not stopped by a locked PMP entry
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6605 In OpenXiangShan/XiangShan;vl=0 unit-stride vector loads (vle8/16/32/64.v, masked and unmasked) wrongly set mstatus.VS to Dirty on kunminghu-v2 — residual load path of #6561
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedversion: kunminghu-v2Issue or PR to the stable release kunminghu-v2Issue or PR to the stable release kunminghu-v2Status: Open.#6602 In OpenXiangShan/XiangShan;vsm.v store access fault reports the base address in mtval instead of the first faulting byte
module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancunversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6599 In OpenXiangShan/XiangShan;Several vector instruction families permanently stall the core (no trap, no commit)
module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6598 In OpenXiangShan/XiangShan;VirtualStoreQueue
retirePtr update error!assertion and a commit stall after a multi-register segmented vector store followed by an AMO (regression between ede751b7c and c8d7b3a5c) — kunminghu-v3module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6597 In OpenXiangShan/XiangShan;A **faulting** segment load with
nf >= 3tripsrobEntries ... uopNum is overflow!module: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedtype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6596 In OpenXiangShan/XiangShan;M-mode
cbo.*to a block denied by a **locked** PMP entry is not trappedmodule: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancuntype: bug/reported(issue) Bug reports to be confirmed(issue) Bug reports to be confirmedStatus: Open.#6595 In OpenXiangShan/XiangShan;vsetivliwith AVL = 0 setsvtype.villwhen it follows an LMUL = 8 configurationmodule: unknownFor bug reports where the faulty module has not yet been locatedFor bug reports where the faulty module has not yet been locatedversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6594 In OpenXiangShan/XiangShan;mtvalis not written on a load access fault taken by a vector strided load (vlse32.v) — kunminghu-v3module: memoryMemblock, DCache, TLB, Prefetcher, coupledL2, huancunMemblock, DCache, TLB, Prefetcher, coupledL2, huancunversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6576 In OpenXiangShan/XiangShan;vssubu.vx(vector fixed-point unsigned saturating subtract) does not setvxsatwhen it saturates — kunminghu-v3module: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6555 In OpenXiangShan/XiangShan;vsrl.vvwithv0.tmask hangs and never writes back the destination registermodule: backendDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanDecode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuanversion: kunminghu-v3Issue or PR to the dev branch kunminghu-v3Issue or PR to the dev branch kunminghu-v3Status: Open.#6545 In OpenXiangShan/XiangShan;