Shlcofideleg extension question #3973
Description
Before start
- I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
- I have read the XiangShan Documents. 我已经阅读过香山文档。
- I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
- I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
- I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。
Describe the question
Describe：
When using spike as a reference model to test Xiangshan, the following inconsistencies occurred
The inconsistency is in the 13th bit of the hideleg register. I found the following explanation in the rsicv specification:
Extension Shlcofideleg supports delegating LCOFI interrupts to VS-mode. If the Shlcofideleg
extension is implemented, hideleg bit 13 is writable; otherwise, it is read-only zero. When bit 13 of
hideleg is zero, vsip.LCOFIP and vsie.LCOFIE are read-only zeros. Else, vsip.LCOFIP and vsie.LCOFIE
are aliases of sip.LCOFIP and sie.LCOFIE.
Has Xiangshan achieved the Shlcofideleg expansion? The extension was not found in the following files
XiangShan/src/main/scala/xiangshan/Parameters.scala
Lines 365 to 377 in 2e5ebf5
Environmental Information
xiangshan:commit fcefab3 (HEAD -> master, origin/master, origin/HEAD)
ready-to-run: commit c1dc496545b9d62bb10264cd4485cb6fe7c60798 (HEAD -> master, origin/master, origin/HEAD)