feat(difftest): refactor transfer logic with ready-valid pipeline #802
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In PR #797, Gateway was switched to use the ungated ref_clock. Before the pipeline-based backpressure support introduced in PR #802, this caused fpga_sim failures. This change temporarily reverts Gateway to use the gated clock to ensure correct behavior. Gateway will switch back to ref_clock after the pipeline refactoring in PR #802 is merged.
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In PR #797, Gateway was switched to use the ungated ref_clock. Before the pipeline-based backpressure support introduced in PR #802, this caused fpga_sim failures. This change temporarily reverts Gateway to use the gated clock to ensure correct behavior. Gateway will switch back to ref_clock after the pipeline refactoring in PR #802 is merged.
This change refactors the Difftest transfer logic to use a ready-valid pipeline for Squash, Batch, Delta, and Diff2AXI. In the updated logic, Delta and Diff2AXI will set the ready signal to 0 when data is not yet processed, applying backpressure to Difftest data. To apply backpressure to data in the Delayer, RegNext is replaced with RegEnable. Additionally, the clockEnable signal is required to remain 0 for an extra cycle compared to the ready signal, ensuring that the valid signal is correctly sampled during the fire handshake process.
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This change refactors the Difftest transfer logic to use a ready-valid pipeline
for Squash, Batch, Delta, and Diff2AXI.
In the updated logic, Delta and Diff2AXI will set the ready signal to 0 when
data is not yet processed, applying backpressure to Difftest data. To apply
backpressure to data in the Delayer, RegNext is replaced with RegEnable.
Additionally, the clockEnable signal is required to remain 0 for an extra
cycle compared to the ready signal, ensuring that the valid signal is correctly
sampled during the fire handshake process.