arch: add code for the Cortex-M33 architecture

This commits adds the code for the Cortex-M33 architecture.
It also adds the possibility to use the Non-Secure alias of the MPU

Author: JADarius

arch/cortex-m/src/mpu.rs

@@ -154,6 +154,15 @@ impl<const NUM_REGIONS: usize, const MIN_REGION_SIZE: usize> MPU<NUM_REGIONS, MI
         }
     }
 
+    // Function for boards that have TrustZone.
+    pub const unsafe fn new_ns() -> Self {
+        Self {
+            registers: MPU_NS_BASE_ADDRESS,
+            config_count: Cell::new(NonZeroUsize::MIN),
+            hardware_is_configured_for: OptionalCell::empty(),
+        }
+    }
+
     // Function useful for boards where the bootloader sets up some
     // MPU configuration that conflicts with Tock's configuration:
     pub unsafe fn clear_mpu(&self) {

arch/cortex-m33/Cargo.toml

@@ -0,0 +1,17 @@
+# Licensed under the Apache License, Version 2.0 or the MIT License.
+# SPDX-License-Identifier: Apache-2.0 OR MIT
+# Copyright Tock Contributors 2022.
+
+[package]
+name = "cortexm33"
+version.workspace = true
+authors.workspace = true
+edition.workspace = true
+
+[dependencies]
+kernel = { path = "../../kernel" }
+cortexm = { path = "../cortex-m" }
+cortexv8m = { path = "../cortex-v8m" }
+
+[lints]
+workspace = true

arch/cortex-m33/README.md

@@ -0,0 +1,5 @@
+Cortex-M33 Architecture
+======================
+
+Architecture support for Cortex-M33 devices. This largely only re-exports the
+correct functions from the Cortex-M crate.

arch/cortex-m33/src/lib.rs

@@ -0,0 +1,61 @@
+// Licensed under the Apache License, Version 2.0 or the MIT License.
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+// Copyright Tock Contributors 2022.
+
+//! Shared implementations for ARM Cortex-M33 MCUs.
+
+#![crate_name = "cortexm33"]
+#![crate_type = "rlib"]
+#![no_std]
+
+use core::fmt::Write;
+
+pub mod mpu {
+    pub type MPU = cortexm::mpu::MPU<16, 32>; // Cortex-M7 MPU has 16 regions
+}
+
+pub use cortexm::initialize_ram_jump_to_main;
+pub use cortexm::interrupt_mask;
+pub use cortexm::nvic;
+pub use cortexm::scb;
+pub use cortexm::support;
+pub use cortexm::systick;
+pub use cortexm::unhandled_interrupt;
+pub use cortexm::CortexMVariant;
+
+// Enum with no variants to ensure that this type is not instantiable. It is
+// only used to pass architecture-specific constants and functions via the
+// `CortexMVariant` trait.
+pub enum CortexM33 {}
+
+impl cortexm::CortexMVariant for CortexM33 {
+    const GENERIC_ISR: unsafe extern "C" fn() = cortexv8m::generic_isr_arm_v8m;
+    const SYSTICK_HANDLER: unsafe extern "C" fn() = cortexv8m::systick_handler_arm_v8m;
+    const SVC_HANDLER: unsafe extern "C" fn() = cortexv8m::svc_handler_arm_v8m;
+    const HARD_FAULT_HANDLER: unsafe extern "C" fn() = cortexv8m::hard_fault_handler_arm_v8m;
+
+    #[cfg(all(target_arch = "arm", target_os = "none"))]
+    unsafe fn switch_to_user(
+        user_stack: *const usize,
+        process_regs: &mut [usize; 8],
+    ) -> *const usize {
+        cortexv8m::switch_to_user_arm_v8m(user_stack, process_regs)
+    }
+
+    #[cfg(not(all(target_arch = "arm", target_os = "none")))]
+    unsafe fn switch_to_user(
+        _user_stack: *const usize,
+        _process_regs: &mut [usize; 8],
+    ) -> *const usize {
+        unimplemented!()
+    }
+
+    #[inline]
+    unsafe fn print_cortexm_state(writer: &mut dyn Write) {
+        cortexm::print_cortexm_state(writer)
+    }
+}
+
+pub mod syscall {
+    pub type SysCall = cortexm::syscall::SysCall<crate::CortexM33>;
+}

arch/cortex-v8m/Cargo.toml

@@ -0,0 +1,15 @@
+# Licensed under the Apache License, Version 2.0 or the MIT License.
+# SPDX-License-Identifier: Apache-2.0 OR MIT
+# Copyright Tock Contributors 2024.
+
+[package]
+name = "cortexv8m"
+version.workspace = true
+authors.workspace = true
+edition.workspace = true
+
+[dependencies]
+kernel = { path = "../../kernel" }
+
+[lints]
+workspace = true

arch/cortex-v8m/README.md

@@ -0,0 +1,10 @@
+Cortex-M v8m Architecture
+=========================
+
+This crate includes shared low-level code for the Cortex-M v8m family of CPU
+architectures.
+
+Boards and chips should not depend on this crate directly. Instead, all of the
+relevant modules and features should be exported through the specific Cortex-M
+crates (e.g. Cortex-M33), and chips and boards should depend on the more specific
+crate.