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theonlytruealextheonlytruealex
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fixed SAES-RNG compatibility- it works. Onto key wrapping tests
1 parent 226ff16 commit b5595fe

6 files changed

Lines changed: 36 additions & 39 deletions

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‎boards/nucleo_u545re_q/src/main.rs‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -160,14 +160,14 @@ unsafe fn start() -> (
160160
stm32u545::aes::Aes<'static, AES256>,
161161
stm32u545::aes::Aes::new(stm32u545::aes::AES_BASE)
162162
);
163-
let saes = static_init!(
164-
stm32u545::saes::Saes<'static, AES256>,
165-
stm32u545::saes::Saes::new(stm32u545::saes::SAES_BASE)
166-
);
167163
let trng = static_init!(
168164
stm32u545::entropy::Trng<'static>,
169165
stm32u545::entropy::Trng::new(stm32u545::entropy::RNG_BASE)
170166
);
167+
let saes = static_init!(
168+
stm32u545::saes::Saes<'static, AES256>,
169+
stm32u545::saes::Saes::new(stm32u545::saes::SAES_BASE, trng)
170+
);
171171

172172
// Load Peripherals Bundle
173173
let periphs = static_init!(

‎capsules/extra/src/test/aes256.rs‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ pub struct TestAES256Ecb<'a, A: 'a> {
5454
source: TakeCell<'static, [u8]>,
5555
data: TakeCell<'static, [u8]>,
5656
test_decrypt: bool,
57+
test_keywrap: Option<usize>,
5758
step: Cell<TestStep>,
5859
client: OptionalCell<&'static dyn CapsuleTestClient>,
5960
}
@@ -65,13 +66,15 @@ impl<'a, A: AES<'a, AES256> + AESECB> TestAES256Ecb<'a, A> {
6566
source: &'static mut [u8],
6667
data: &'static mut [u8],
6768
test_decrypt: bool,
69+
test_keywrap: Option<usize>,
6870
) -> Self {
6971
TestAES256Ecb {
7072
aes,
7173
key: TakeCell::new(key),
7274
source: TakeCell::new(source),
7375
data: TakeCell::new(data),
7476
test_decrypt,
77+
test_keywrap,
7578
step: Cell::new(TestStep::StandardEnc),
7679
client: OptionalCell::empty(),
7780
}
@@ -207,7 +210,6 @@ impl<'a, A: AES<'a, AES256> + AESCBC> TestAES256Cbc<'a, A> {
207210

208211
let (start, stop) = chunk_range(step);
209212
run_crypt(self.aes, in_place, &self.source, &self.data, start, stop);
210-
debug!("ran");
211213
}
212214
}
213215

‎chips/stm32u5xx/src/chip.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ use crate::nvic::{
99
AES_IRQ, EXTI13_IRQ, GPDMA1_CH0_IRQ, GPDMA1_CH10_IRQ, GPDMA1_CH11_IRQ, GPDMA1_CH12_IRQ,
1010
GPDMA1_CH13_IRQ, GPDMA1_CH14_IRQ, GPDMA1_CH15_IRQ, GPDMA1_CH1_IRQ, GPDMA1_CH2_IRQ,
1111
GPDMA1_CH3_IRQ, GPDMA1_CH4_IRQ, GPDMA1_CH5_IRQ, GPDMA1_CH6_IRQ, GPDMA1_CH7_IRQ, GPDMA1_CH8_IRQ,
12-
GPDMA1_CH9_IRQ, SAES_IRQ, TIM2_IRQ, USART1_IRQ,
12+
GPDMA1_CH9_IRQ, RNG_IRQ, SAES_IRQ, TIM2_IRQ, USART1_IRQ,
1313
};
1414
use crate::rcc;
1515
use crate::tim;

‎chips/stm32u5xx/src/entropy.rs‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,10 @@ impl<'a> Trng<'a> {
157157
}
158158
}
159159
}
160+
161+
pub fn is_enabled(&self) -> bool {
162+
self.registers.cr.is_set(CR::RNGEN)
163+
}
160164
}
161165

162166
impl<'a> Entropy32<'a> for Trng<'a> {

‎chips/stm32u5xx/src/rcc.rs‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use kernel::utilities::StaticRef;
1010
register_structs! {
1111
pub RccRegisters {
1212
/// Control register
13-
(0x000 => cr: ReadWrite<u32>),
13+
(0x000 => cr: ReadWrite<u32, CR::Register>),
1414
(0x004 => _reserved0: [u32; 33]),
1515
/// AHB1 peripheral clock enable register
1616
(0x088 => ahb1enr: ReadWrite<u32, AHB1ENR::Register>),
@@ -27,11 +27,16 @@ register_structs! {
2727
(0x0AC => _reserved3: [u32; 13]),
2828
/// Peripherals independent clock configuration register 1
2929
(0x0E0 => ccipr1: ReadWrite<u32, CCIPR1::Register>),
30+
/// Peripherals independent clock configuration register 2
3031
(0x0E4 => @END),
3132
}
3233
}
3334

3435
register_bitfields![u32,
36+
pub CR[
37+
SHSION OFFSET(14) NUMBITS(1)[],
38+
SHSIRDY OFFSET(15) NUMBITS(1)[],
39+
],
3540
pub AHB1ENR [
3641
GPDMA1EN OFFSET(0) NUMBITS(1) []
3742
],
@@ -107,6 +112,7 @@ impl Rcc {
107112
}
108113

109114
pub fn enable_saes(&self) {
115+
self.registers.cr.modify(CR::SHSION::SET);
110116
self.registers.ahb2enr1.modify(AHB2ENR1::SAESEN::SET);
111117
}
112118

‎chips/stm32u5xx/src/saes.rs‎

Lines changed: 17 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
33
use kernel::debug;
44
use kernel::errorcode::ErrorCode;
55
use kernel::hil::symmetric_encryption::{
6-
AESKey, AESKeySize, AES, AES128_KEY_SIZE, AES_BLOCK_SIZE, AES_IV_SIZE,
6+
AESKey, AESKeySize, AES, AES128_KEY_SIZE, AES256_KEY_SIZE, AES_BLOCK_SIZE, AES_IV_SIZE,
77
};
88
use kernel::utilities::cells::{OptionalCell, TakeCell};
99
use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable};
@@ -13,6 +13,8 @@ use kernel::utilities::registers::{
1313

1414
use kernel::utilities::StaticRef;
1515

16+
use crate::entropy::Trng;
17+
1618
register_structs! {
1719
/// Secure AES coprocessor
1820
pub SaesRegisters {
@@ -236,7 +238,7 @@ pub struct Saes<'a, K: AESKeySize> {
236238
}
237239

238240
impl<'a, K: AESKeySize> Saes<'a, K> {
239-
pub fn new(base: StaticRef<SaesRegisters>) -> Saes<'a, K> {
241+
pub fn new(base: StaticRef<SaesRegisters>, _trng: &'static Trng) -> Saes<'a, K> {
240242
Saes {
241243
registers: base,
242244
mode: Cell::new(SAESMode::ECB),
@@ -269,23 +271,23 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
269271
/// Helper to write a 128-bit or 256-bit key into the hardware key registers
270272
fn write_key_registers(&self, key: &[u8]) {
271273
// Default to using the first 16 bytes for the lower registers (AES-128 behavior)
272-
let mut lower_key_chunk = &key[0..16];
274+
let mut lower_key_chunk = &key[0..AES128_KEY_SIZE];
273275

274-
if K::LENGTH == 32 {
276+
if K::LENGTH == AES256_KEY_SIZE {
275277
// AES-256: Write KEYR7 down to KEYR4 first
276278
for (reg, chunk) in self
277279
.registers
278280
.keyr2
279281
.iter()
280282
.rev()
281-
.zip(key[0..16].chunks_exact(4))
283+
.zip(key[0..AES128_KEY_SIZE].chunks_exact(4))
282284
{
283285
let word = u32::from_be_bytes(chunk.try_into().unwrap());
284286
reg.write(Data::DATA.val(word));
285287
}
286288

287289
// Update the slice so the lower registers get the second half of the 256-bit key
288-
lower_key_chunk = &key[16..32];
290+
lower_key_chunk = &key[AES128_KEY_SIZE..AES256_KEY_SIZE];
289291
}
290292

291293
// Write KEYR3 down to KEYR0
@@ -354,7 +356,7 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
354356
let mut block = [0u8; AES_BLOCK_SIZE];
355357
for chunk in block.chunks_exact_mut(4) {
356358
let word = self.registers.doutr.get();
357-
chunk.copy_from_slice(&word.to_le_bytes());
359+
chunk.copy_from_slice(&word.to_be_bytes());
358360
}
359361
block
360362
}
@@ -365,19 +367,16 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
365367
self.registers.cr.modify(CR::EN::SET);
366368
}
367369
self.write_input(ctx);
368-
debug!("wrote input");
369-
debug!("CR: {:02x?}", self.registers.cr.get());
370-
debug!("SR: {:02x?}", self.registers.sr.get());
371370
}
372371

373372
fn start_key_wrapping(&self, ctx: CryptoContext, key_id: KeyID) {
374373
let regs = self.registers;
375374

376375
match K::LENGTH {
377-
16 => {
376+
AES128_KEY_SIZE => {
378377
regs.cr.modify(CR::KEYSIZE::AES128);
379378
}
380-
32 => {
379+
AES256_KEY_SIZE => {
381380
regs.cr.modify(CR::KEYSIZE::AES256);
382381
}
383382
_ => {}
@@ -444,11 +443,7 @@ impl<'a, K: AESKeySize> Saes<'a, K> {
444443
}
445444

446445
pub fn handle_interrupt(&self) {
447-
debug!("INTERRUPT");
448-
debug!("CR: {:02x?}", self.registers.cr.get());
449-
debug!("SR: {:02x?}", self.registers.sr.get());
450446
if self.registers.isr.is_set(ISR::CCF) {
451-
debug!("CCF");
452447
self.registers.icr.write(ICR::CCF::SET);
453448
self.computation_complete();
454449
}
@@ -474,12 +469,9 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
474469
fn enable(&self) {
475470
self.registers.cr.modify(CR::IPRST::SET);
476471
self.registers.cr.write(CR::EN::CLEAR);
477-
self.registers.cr.modify(CR::DATATYPE::Byte);
472+
self.registers.cr.modify(CR::DATATYPE::None);
478473
self.state.set(State::Idle);
479474
self.enable_interrupts();
480-
debug!("ENABLE");
481-
debug!("CR: {:02x?}", self.registers.cr.get());
482-
debug!("SR: {:02x?}", self.registers.sr.get());
483475
}
484476

485477
fn disable(&self) {
@@ -494,9 +486,6 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
494486
}
495487

496488
fn set_key(&self, key: AESKey) -> Result<(), ErrorCode> {
497-
debug!("KEY");
498-
debug!("CR: {:02x?}", self.registers.cr.get());
499-
debug!("SR: {:02x?}", self.registers.sr.get());
500489
if self.registers.cr.any_matching_bits_set(CR::EN::SET)
501490
|| self.registers.sr.any_matching_bits_set(SR::BUSY::SET)
502491
{
@@ -522,7 +511,7 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
522511
return Err(ErrorCode::INVAL);
523512
}
524513

525-
if K::LENGTH == 16 {
514+
if K::LENGTH == AES128_KEY_SIZE {
526515
self.registers.cr.modify(CR::KEYSIZE::AES128);
527516
} else {
528517
self.registers.cr.modify(CR::KEYSIZE::AES256);
@@ -542,14 +531,13 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
542531
}
543532

544533
fn set_iv(&self, iv: &[u8]) -> Result<(), ErrorCode> {
545-
debug!("IV");
546-
debug!("CR: {:02x?}", self.registers.cr.get());
547-
debug!("SR: {:02x?}", self.registers.sr.get());
548534
if iv.len() != AES_IV_SIZE {
549535
return Err(ErrorCode::INVAL);
550536
}
551537

552-
if self.registers.cr.any_matching_bits_set(CR::EN::SET) {
538+
if self.registers.cr.any_matching_bits_set(CR::EN::SET)
539+
|| self.registers.sr.any_matching_bits_set(SR::BUSY::SET)
540+
{
553541
return Err(ErrorCode::BUSY);
554542
}
555543

@@ -578,13 +566,10 @@ impl<'a, K: AESKeySize> kernel::hil::symmetric_encryption::AES<'a, K> for Saes<'
578566
Option<&'static mut [u8]>,
579567
&'static mut [u8],
580568
)> {
581-
debug!("CRYPT");
582-
debug!("CR: {:02x?}", self.registers.cr.get());
583-
debug!("SR: {:02x?}", self.registers.sr.get());
584569
let state = self.state.get();
585570

586571
// Hardware busy check
587-
if self.output.is_some() {
572+
if self.output.is_some() || self.registers.sr.any_matching_bits_set(SR::BUSY::SET) {
588573
return Some((Err(ErrorCode::BUSY), source, dest));
589574
}
590575

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