Backline is an open platform for compilation and low-latency execution by AMD and Xanadu that dynamically connects quantum workloads to the right classical engine.
With PennyLane and Backline, anyone can write a QEC encoder or decoder from Python, test it with meaningful quantum algorithms, and immediately deploy it for near-real-time execution on CPUs, GPUs, FPGAs, and QPUs — while supporting the need to drop through abstractions and write increasingly optimized and low-level code.
Note
The core Backline implementation and source code lives natively within the PennyLane and Catalyst repositories. This repository holds the demonstrations, benchmarks, and the cross-build system accompanying the manuscript "Python in the front, party in the Backline: compiling quantum workloads across CPUs, GPUs, and FPGAs".
Note
Backline is currently under heavy development — if you have suggestions on the API or use-cases you'd like covered, please open a GitHub issue in the relevant repository (PennyLane or Catalyst), or reach out to quantum@amd.com and backline@xanadu.ai. We'd love to hear about how you're using the library, collaborate on development, or integrate additional devices and frontends.
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Single-digit microsecond latency: Achieve under 3-μs end-to-end loops. Backline treats CPUs and GPUs as highly responsive endpoints to support the tight co-processing needed for QEC backup decoding.
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Scale from R&D to production: Prototype immediately on standard CPUs—bypassing the need for any GPUs. Then, seamlessly scale to consumer- and enterprise-grade GPUs and FPGAs from the exact same PennyLane application.
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Python-native: Build entirely in Python. Write optimized GPU kernels using Triton and Gluon, or integrate pre-compiled libraries alongside your quantum logic. Easily jump through abstraction layers without switching frameworks.
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Infrastructure agnostic by design: Leveraging the LLVM ecosystem, Backline supports CPUs, GPUs, FPGAs, and custom devices to meet the diverse error-correction needs of any quantum platform.
Once Backline is installed, you can get started by checking out the Backline tutorial, then working your way through the demos in this repository. To reproduce the paper, run those and the benchmarks.
Also make sure to check out the technical documentation, technical manuscript, and Backline whitepaper.
Backline provides the following three main abstractions for use with PennyLane and Catalyst:
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Controllers: This is the classical hardware node (such as a CPU or FPGA) that controls the QPU (a quantum hardware or simulator
qp.device), receives quantum measurement results, and initiates data transfers with other hardware devices (coprocessors). For example, it might perform QEC syndrome measurements on the QPU, and send these to a coprocessor for decoding. -
Coprocessors: These are hardware device nodes (such as CPUs, GPUs, or FPGAs) that receive information from a controller for processing. They run specific coprocessing functions, potentially as a persistent kernel, such as a QEC decoder.
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Backline: A representation of the complete hardware infrastructure supporting the quantum-classical program. The backline includes a controller, one or more coprocessors, and a transport method. A backline object is given directly to a QNode in place of a traditional QNode
qp.device, and orchestrates the remote executor and the RDMA network the controllers and coprocessors talk over, separate from the network used to log into remote machines.
If you are an AI agent, read AGENTS.md first: the same material, plus the specific
traps that have caught agents here before.
This repository contains the benchmark data from the manuscript "Python in the front, party in the Backline: compiling quantum workloads across CPUs, GPUs, and FPGAs", as well as the cross-build system for reproducing the stack demonstrated.
In addition, a variety of demos are provided, highlighting the compilation, deployment, and execution of a single quantum error-corrected PennyLane program onto several machines at once with low-latency execution.
benchmarks: the latency measurements the manuscript reports.config: the cross-build system (xbuild) and the machines to run on (machines.toml) to reproduce the results from the manuscript.data: the measurements themselves, and the notebook to plot.demos: demo programs, spanning from a single CPU machine to FPGA-to-GPU.scripts: helpers for running the above.
Backline requires a recent version of PennyLane, Catalyst, and Lightning. We
recommend installing version v0.46.0b1 for PennyLane and Lightning, v0.16.0b1 for Catalyst (either from source or using pre-built wheels for local demos).
To install Backline, please see INSTALL.md for instructions and requirements. Note
that due to the wide range of system, network, and hardware configurations you can use Backline
with, there are different installation requirements and steps depending on your needs:
| Tier | Features and usage | Requirements | Corresponding Demo |
|---|---|---|---|
| 1 | Local CPU-CPU interactions on any Linux CPU machine | PennyLane and Catalyst | 1 |
| 2 | Local CPU-CPU interactions over RDMA | As above, plus a device that supports the libibverbs interface; soft-RoCE will do, an RDMA NIC is optional |
1a |
| 3 | Remote CPU-GPU interactions | As above, plus a server containing a GPU and an RDMA NIC, accessible over SSH | 2, 2a, 3 |
| 4 | Remote CPU-FPGA or GPU-FPGA interactions | As above, plus a Xilinx VPK120 board connected to the server via RDMA | 4, 5, benchmarks |
Once Backline is installed, you can verify your installation locally by compiling and executing a simple local CPU-CPU interactions on a Linux CPU machine via memcpy.
Two environment variables to be aware of when using Backline are:
CATALYST_ROOT: the local Catalyst build tree, default~/catalyst.BACKLINE_BUNDLES: the cross-built stacks the remote machines deploy, one directory per bundle name. Defaults to whatconfig/xbuildpublishes.
Backline is the work of many contributors.
If you are doing research using Backline and PennyLane, please cite our papers:
@article{tk,
title={Python in the front, party in the Backline: compiling quantum workloads across CPUs, GPUs, and FPGAs},
author={Joseph K. L. Lee and Mehrdad Malekmohammadi and Hong-Sheng Zheng and Shuli Shu and Cheick Doumbia and Kalman Szenes Mehran Zamani Abnili and Thomas Ainsworth and Matthew Seymour and Thomas Germain and Leonhard Neuhaus and Josh Izaac and Lee J. O'Riordan},
journal={arXiv preprint arXiv:tk},
year={2026}
}
Backline is free and open source, released under the Apache License, Version 2.0.
AMD, AMD Ryzen, AMD Ryzen Threadripper, AMD Instinct, AMD ROCm, Radeon, Versal, and Xilinx are trademarks of Advanced Micro Devices, Inc.