Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Python-based Hardware Design Processing Toolkit for Verilog HDL

Automatic Hardware Design Translator for Checkpointing and Live Migration on FPGAs

IP-core package generator for AXI4/Avalon

How to configure Debian Linux environment for Xilinx Zynq.

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms

MULPY: A Multi-Paradigm High-Level Hardware Design Framework in Python