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Merge branch 'fix_stubmodule' into develop
2 parents 7240d45 + 4f87a64 commit 06b3490

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8 files changed

+343
-6
lines changed

8 files changed

+343
-6
lines changed

‎tests/core/stub_/str/stub_str.py

+1-6
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,14 @@
1111
from veriloggen import *
1212

1313

14-
def mkLed():
15-
m = StubModule('blinkled')
16-
return m
17-
18-
1914
def mkTop():
2015
m = Module('top')
2116
width = m.Parameter('WIDTH', 8)
2217
clk = m.Input('CLK')
2318
rst = m.Input('RST')
2419
led = m.Output('LED', width)
2520

26-
params = (width, )
21+
params = (width,)
2722
ports = (clk, rst, led)
2823

2924
# StubModule is automatically created inside

‎tests/core/stub_/str_multiple/Makefile

+29
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
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all: test
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.PHONY: run
14+
run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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17+
.PHONY: test
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test:
19+
$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
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check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

‎tests/core/stub_/str_multiple/stub_str_multiple.py

+36
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
import collections
6+
7+
# the next line can be removed after installation
8+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
9+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
10+
11+
from veriloggen import *
12+
13+
14+
def mkTop():
15+
m = Module('top')
16+
width = m.Parameter('WIDTH', 8)
17+
clk = m.Input('CLK')
18+
rst = m.Input('RST')
19+
led0 = m.Output('LED0', width)
20+
led1 = m.Output('LED1', width)
21+
22+
params0 = (width,)
23+
ports0 = (clk, rst, led0)
24+
m.Instance('blinkled', 'inst_blinkled0', params0, ports0)
25+
26+
params1 = (width,)
27+
ports1 = (clk, rst, led1)
28+
m.Instance('blinkled', 'inst_blinkled1', params0, ports1)
29+
30+
return m
31+
32+
33+
if __name__ == '__main__':
34+
top = mkTop()
35+
verilog = top.to_verilog()
36+
print(verilog)

‎tests/core/stub_/str_multiple/test_stub_str_multiple.py

+60
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import veriloggen
4+
import stub_str_multiple
5+
6+
7+
expected_verilog = """
8+
module top #
9+
(
10+
parameter WIDTH = 8
11+
)
12+
(
13+
input CLK,
14+
input RST,
15+
output [WIDTH-1:0] LED0,
16+
output [WIDTH-1:0] LED1
17+
);
18+
19+
20+
blinkled
21+
#(
22+
WIDTH
23+
)
24+
inst_blinkled0
25+
(
26+
CLK,
27+
RST,
28+
LED0
29+
);
30+
31+
32+
blinkled
33+
#(
34+
WIDTH
35+
)
36+
inst_blinkled1
37+
(
38+
CLK,
39+
RST,
40+
LED1
41+
);
42+
43+
44+
endmodule
45+
"""
46+
47+
48+
def test():
49+
veriloggen.reset()
50+
test_module = stub_str_multiple.mkTop()
51+
code = test_module.to_verilog()
52+
53+
from pyverilog.vparser.parser import VerilogParser
54+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
55+
parser = VerilogParser()
56+
expected_ast = parser.parse(expected_verilog)
57+
codegen = ASTCodeGenerator()
58+
expected_code = codegen.visit(expected_ast)
59+
60+
assert(expected_code == code)

‎tests/core/stub_/withcode_multiple/Makefile

+29
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: run
14+
run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
16+
17+
.PHONY: test
18+
test:
19+
$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
22+
check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

‎tests/core/stub_/withcode_multiple/stub_withcode_multiple.py

+84
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
import collections
6+
7+
# the next line can be removed after installation
8+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
9+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
10+
11+
from veriloggen import *
12+
13+
stubcode = """\
14+
15+
16+
module blinkled #
17+
(
18+
parameter WIDTH = 8
19+
)
20+
(
21+
input CLK,
22+
input RST,
23+
output reg [WIDTH-1:0] LED
24+
);
25+
26+
reg [32-1:0] count;
27+
28+
always @(posedge CLK) begin
29+
if(RST) begin
30+
count <= 0;
31+
end else begin
32+
if(count == 1023) begin
33+
count <= 0;
34+
end else begin
35+
count <= count + 1;
36+
end
37+
end
38+
end
39+
40+
41+
always @(posedge CLK) begin
42+
if(RST) begin
43+
LED <= 0;
44+
end else begin
45+
if(count == 1023) begin
46+
LED <= LED + 1;
47+
end
48+
end
49+
end
50+
51+
52+
endmodule
53+
54+
"""
55+
56+
57+
def mkLed():
58+
m = StubModule('blinkled', code=stubcode)
59+
return m
60+
61+
62+
def mkTop():
63+
m = Module('top')
64+
width = m.Parameter('WIDTH', 8)
65+
clk = m.Input('CLK')
66+
rst = m.Input('RST')
67+
led0 = m.Output('LED0', width)
68+
led1 = m.Output('LED1', width)
69+
70+
params0 = (width,)
71+
ports0 = (clk, rst, led0)
72+
m.Instance(mkLed(), 'inst_blinkled0', params0, ports0)
73+
74+
params1 = (width,)
75+
ports1 = (clk, rst, led1)
76+
m.Instance(mkLed(), 'inst_blinkled1', params1, ports1)
77+
78+
return m
79+
80+
81+
if __name__ == '__main__':
82+
top = mkTop()
83+
verilog = top.to_verilog()
84+
print(verilog)

‎tests/core/stub_/withcode_multiple/test_stub_withcode_multiple.py

+99
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,99 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import veriloggen
4+
import stub_withcode_multiple
5+
6+
expected_verilog = """
7+
module top #
8+
(
9+
parameter WIDTH = 8
10+
)
11+
(
12+
input CLK,
13+
input RST,
14+
output [WIDTH-1:0] LED0,
15+
output [WIDTH-1:0] LED1
16+
);
17+
18+
19+
blinkled
20+
#(
21+
WIDTH
22+
)
23+
inst_blinkled0
24+
(
25+
CLK,
26+
RST,
27+
LED0
28+
);
29+
30+
31+
blinkled
32+
#(
33+
WIDTH
34+
)
35+
inst_blinkled1
36+
(
37+
CLK,
38+
RST,
39+
LED1
40+
);
41+
42+
43+
endmodule
44+
45+
46+
47+
module blinkled #
48+
(
49+
parameter WIDTH = 8
50+
)
51+
(
52+
input CLK,
53+
input RST,
54+
output reg [WIDTH-1:0] LED
55+
);
56+
57+
reg [32-1:0] count;
58+
59+
always @(posedge CLK) begin
60+
if(RST) begin
61+
count <= 0;
62+
end else begin
63+
if(count == 1023) begin
64+
count <= 0;
65+
end else begin
66+
count <= count + 1;
67+
end
68+
end
69+
end
70+
71+
72+
always @(posedge CLK) begin
73+
if(RST) begin
74+
LED <= 0;
75+
end else begin
76+
if(count == 1023) begin
77+
LED <= LED + 1;
78+
end
79+
end
80+
end
81+
82+
83+
endmodule
84+
"""
85+
86+
87+
def test():
88+
veriloggen.reset()
89+
test_module = stub_withcode_multiple.mkTop()
90+
code = test_module.to_verilog()
91+
92+
from pyverilog.vparser.parser import VerilogParser
93+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
94+
parser = VerilogParser()
95+
expected_ast = parser.parse(expected_verilog)
96+
codegen = ASTCodeGenerator()
97+
expected_code = codegen.visit(expected_ast)
98+
99+
assert(expected_code == code)

‎veriloggen/core/module.py

+5
Original file line numberDiff line numberDiff line change
@@ -1296,6 +1296,11 @@ def check_existing_identifier(self, name, *types):
12961296
class StubModule(vtypes.VeriloggenNode):
12971297
""" Verilog Module class """
12981298

1299+
def __eq__(self, other):
1300+
if isinstance(other, StubModule):
1301+
return (self.name == other.name and self.code == other.code)
1302+
return False
1303+
12991304
def __init__(self, name=None, code=''):
13001305
vtypes.VeriloggenNode.__init__(self)
13011306
self.name = name if name is not None else self.__class__.__name__

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