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8184c40
feat(moe): Replace A4W4 GEMM1 with MXFP4 kernel
fsx950223 Jul 30, 2026
951fafd
feat(moe): Add activation dtype to MXFP4 GEMM1
fsx950223 Jul 30, 2026
b7b882e
perf(moe): Update GLM-5 FP4 tuned config
fsx950223 Jul 30, 2026
71e1ed7
perf(moe): Tune GLM-5 MXFP4 tile selection
fsx950223 Jul 31, 2026
2c8a555
feat(moe): Extend MXFP4 GEMM1 replacement to A8W4
fsx950223 Aug 3, 2026
1a2b201
perf(moe): Optimize MXFP4 GEMM1 data movement
fsx950223 Aug 3, 2026
8d0d469
Merge remote-tracking branch 'origin/main' into cursor-merge-main-pr4…
fsx950223 Aug 3, 2026
0936616
Merge latest main into A8W4 replacement
fsx950223 Aug 4, 2026
6bb7489
ci: apply Black 26.5 formatting
fsx950223 Aug 4, 2026
b87f2a2
perf(moe): Tune A4W4 configs with MXFP4 GEMM1
fsx950223 Aug 4, 2026
388f7fb
fix(moe): Complete A4W4 GEMM1 config migration
fsx950223 Aug 4, 2026
f9005dd
revert(moe): Restore A8W4 tuned configs
fsx950223 Aug 4, 2026
501519e
ci: satisfy Ruff startswith check
fsx950223 Aug 4, 2026
d4e695e
perf(moe): Keep MXFP4 intermediates sorted
fsx950223 Aug 4, 2026
974cc2c
perf(moe): Simplify MXFP4 GEMM1 launch setup
fsx950223 Aug 4, 2026
ded5ae0
refactor(moe): Simplify MXFP4 activation names
fsx950223 Aug 4, 2026
fe5cdb6
refactor(moe): Decouple activation values from kernel names
fsx950223 Aug 4, 2026
d2b3618
perf(moe): Optimize MXFP4 GEMM1 LDS access
fsx950223 Aug 5, 2026
3bbcff1
refactor(moe): Simplify MXFP4 GEMM1 compile setup
fsx950223 Aug 6, 2026
887e34d
feat(moe): Support MXFP4 GEMM1 v2 output layout
fsx950223 Aug 6, 2026
8047611
Merge remote-tracking branch 'origin/main' into worktree-main-2026072…
fsx950223 Aug 6, 2026
3509f62
ci: fix Ruff failures after main merge
fsx950223 Aug 6, 2026
cb06643
Merge latest main into worktree-main-20260727-0752
fsx950223 Aug 11, 2026
ec12cf0
chore(moe): Limit PR to MoE changes
fsx950223 Aug 12, 2026
11fc778
fix(moe): Precompile dynamically replaced GEMM2
fsx950223 Aug 12, 2026
5085a10
Merge latest main into worktree-main-20260727-0752
fsx950223 Aug 12, 2026
d351535
feat(moe): support interleaved BN128 MXFP4 GEMM1
fsx950223 Aug 7, 2026
7e9bbf2
feat(moe): optimize small-N MXFP4 GEMM1
fsx950223 Aug 12, 2026
37b31c2
perf(moe): tune Kimi K3 A4W4 layout GEMM2
fsx950223 Aug 12, 2026
919209b
fix(moe): preserve activation in MXFP4 tuning
fsx950223 Aug 12, 2026
c6e8088
fix(moe): honor tuned MXFP4 configs
fsx950223 Aug 12, 2026
275042e
perf(moe): tune Kimi K3 A4W4 GEMM1
fsx950223 Aug 12, 2026
fa3f138
chore(moe): remove redundant MXFP4 tuner wrapper
fsx950223 Aug 12, 2026
343ac88
refactor(moe): revert MXFP4 tuner extensions
fsx950223 Aug 12, 2026
1049163
fix(moe): align BM16 MXFP4 GEMM1 scale layout
fsx950223 Aug 13, 2026
bfa623c
Merge latest main into worktree-main-20260727-0752
fsx950223 Aug 13, 2026
82612d2
perf(moe): retune FP4 GEMM1 model configs
fsx950223 Aug 13, 2026
ca6dbaf
fix(moe): use logical width for GEMM1 AOT cache
fsx950223 Aug 14, 2026
fa062ad
feat(moe): add MXFP4 GEMM1 k-wave support
fsx950223 Aug 14, 2026
9f88a1e
fix(moe): preserve reverse map for native GEMM2 reduce
fsx950223 Aug 17, 2026
81c01d6
Merge latest main into worktree-main-20260727-0752
fsx950223 Aug 17, 2026
36c7e39
[Misc] Revert stray edit to gfx950 gluon mla.py
fsx950223 Aug 17, 2026
f07c272
fix(moe): align GEMM1 AOT specialization with runtime
fsx950223 Aug 17, 2026
cca92ba
[Kernel] Relax two over-conservative GEMM1 guards
fsx950223 Aug 19, 2026
e795d6c
[Kernel] Hoist the GEMM1 bias load out of the epilogue M loop
fsx950223 Aug 19, 2026
f534fa8
Merge branch 'main' into worktree-main-20260727-0752
fsx950223 Aug 20, 2026
b94033e
[Kernel] Replace arith.minsi with the fx ternary-select idiom
fsx950223 Aug 20, 2026
3efbd43
[Kernel] Bound the GEMM1 B-scale load by B_SCALE_REPS
fsx950223 Aug 20, 2026
e0430fb
[Kernel] Revert FP4 fmoe configs and apply the latest MXFP4 GEMM1 sweep
fsx950223 Aug 21, 2026
2100e9c
[Kernel] Finish reverting the FP4 fmoe configs to main
fsx950223 Aug 21, 2026
4616bfb
[Kernel] Drop the wide-MFMA GEMM1 prototype
fsx950223 Aug 21, 2026
fcc5165
[Bugfix] Bind MXFP4 GEMM1 interleave to gate_mode, not the kernel name
fsx950223 Aug 24, 2026
c16f63a
[Perf] Drop the per-call A-scale zero_ from MXFP4 GEMM1
fsx950223 Aug 25, 2026
ec25013
[Perf] Restore the fused MXFP4 sort prologue for atomic-GEMM2 configs
fsx950223 Aug 25, 2026
c3af06d
Merge branch 'main' into worktree-main-20260727-0752
fsx950223 Aug 26, 2026
ca52fac
[Config] Drop the unreachable `_il` tag from MXFP4 GEMM1 rows
fsx950223 Aug 26, 2026
61c306c
[Perf] Let output_aux pick the MXFP4 a4w4 prologue, and add an Opus one
fsx950223 Aug 26, 2026
31f03bc
[Perf] Default MXFP4 aux sorting to Opus and retune Kimi-K3
fsx950223 Aug 27, 2026
b562377
Merge branch 'main' into worktree-main-20260727-0752
fsx950223 Aug 27, 2026
35aa684
[Perf] Reuse fused MXFP4 scale prep in Opus pipeline
fsx950223 Aug 27, 2026
4548384
[Bugfix] Align BM16 MXFP4 scale layout with GEMM2
fsx950223 Aug 28, 2026
777072a
Merge latest main into worktree-main-20260727-0752
fsx950223 Aug 28, 2026
bf76481
[Bugfix] Enable FP8 stage2 for MXFP4 GEMM1
fsx950223 Aug 28, 2026
a86dfd9
[Perf] Default MXFP4 auxiliary sorting to Opus
fsx950223 Aug 28, 2026
90b634c
[Bugfix] Align MXFP4 AOT with supported pipelines
fsx950223 Aug 28, 2026
8d49b61
[Test] Remove MXFP4 AOT parser test
fsx950223 Aug 28, 2026
a91941c
[Refactor] Simplify MXFP4 stage2 forwarding
fsx950223 Aug 28, 2026
e610587
[Refactor] Trim MXFP4 MoE comments
fsx950223 Aug 28, 2026
ba12497
[Bugfix] Address MXFP4 MoE review: scale layout, bias, AOT keys
fsx950223 Aug 31, 2026
5832c06
[FlyDSL] Add MXFP4 GEMM1 hidden prefetch and retune kimik3 a4w4
fsx950223 Aug 31, 2026
2635391
[Test] Remove MXFP4 MoE review regression tests
fsx950223 Aug 31, 2026
d3dabe7
[Tuner] Extend the MXFP4 GEMM1 tuning space and fix its accuracy gate
fsx950223 Aug 31, 2026
f7dffe6
change _port_e2e aux to opus
fsx950223 Aug 31, 2026
9355c59
[Tuner] Pass the SiTUv2 betas from run_config to fused_moe
fsx950223 Sep 1, 2026
5b10527
[Perf] Send block_m 16 MXFP4 a4w4 to the Opus auxiliary sort
fsx950223 Sep 1, 2026
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2 changes: 2 additions & 0 deletions aiter/aot/flydsl/fhmoe.py
Original file line number Diff line number Diff line change
Expand Up @@ -92,6 +92,7 @@ def build_stage2_args(
sorted_weights,
num_valid_ids,
token_num,
x_rows,
n_in,
k_in,
blocks,
Expand All @@ -114,6 +115,7 @@ def build_stage2_args(
sorted_weights,
num_valid_ids,
token_num,
x_rows,
n_in,
k_in,
blocks,
Expand Down
10 changes: 5 additions & 5 deletions aiter/aot/flydsl/moe.py
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ def parse_csv(csv_path: str):
}
if shared_expert_id >= 0:
job["shared_expert_id"] = shared_expert_id
# Stage2 needs to know whether stage1 fuses fp4/fp8 quant
# Stage2 needs to know whether stage1 fuses fp4/fp8 quant --
# this changes the shape of a2_scale (sorted scale buffer
# vs separate quant call output).
if params["stage"] == 2:
Expand Down Expand Up @@ -352,7 +352,7 @@ def _make_a2_scale_for_stage2():
"""Stage2 a2_scale construction per fused_moe_2stages.

When upstream stage1 fuses fp4/fp8 quant (``stage1_fuse_quant`` set),
stage2 receives stage1's ``out_scale_sorted`` buffer directly that
stage2 receives stage1's ``out_scale_sorted`` buffer directly -- that
buffer is padded to 256 rows and 8 cols. Otherwise stage2 quantizes
its own input and the resulting sorted scale uses 32-row alignment.
"""
Expand Down Expand Up @@ -397,7 +397,7 @@ def _make_a2_scale_for_stage2():
return None

def _make_w_scale(scale_storage_numel: int):
# mxfp4 e8m0 scale viewed as uint8 by _view_safe before kernel launch.
# mxfp4 e8m0 scale -- viewed as uint8 by _view_safe before kernel launch.
return torch.zeros(scale_storage_numel, dtype=torch.uint8, device=dev)

def _make_a_user(a_dtype_user_shape):
Expand Down Expand Up @@ -669,7 +669,6 @@ def _make_a_user(a_dtype_user_shape):
# inter_dim=384), in which case runtime compiles the legal fallback.
tile_k = resolve_flydsl_stage2_tile_k(inter_dim, tile_k)

# Stage2 input is (token_num, topk, inter_dim) in a_dtype storage.
if a_dtype == "fp4":
a_shape = (tokens, topk, inter_dim // 2)
else:
Expand Down Expand Up @@ -755,6 +754,7 @@ def _make_a_user(a_dtype_user_shape):
sw_arg,
num_valid_ids,
tokens,
tokens * topk,
_n_in,
_k_in,
m_blocks,
Expand Down Expand Up @@ -851,7 +851,7 @@ def _precompile_a16w4_to_cache(
The port launch ABI (raw fx.Int64 device pointers) differs from the generic MX
gemm (``_s1_args_fp4``), so it can't reuse ``_precompile_to_cache``'s arg
builders. Instead drive the SAME runtime launchers (``flydsl_a16w4_gemm{1,2}``)
the fused-MoE op uses, under ``COMPILE_ONLY=1`` the cache key then matches
the fused-MoE op uses, under ``COMPILE_ONLY=1`` -- the cache key then matches
runtime by construction (``waves_per_eu=None``, ``persist=False``,
``w_layout="standard"``, g2 tile downgrade are all applied inside the
launcher). The compiled artifact is keyed only on the kernel's constexpr
Expand Down
122 changes: 96 additions & 26 deletions aiter/aot/flydsl/mxfp4_moe.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: MIT
# Copyright (C) 2024-2026, Advanced Micro Devices, Inc. All rights reserved.

"""AOT pre-compile for FlyDSL mxmoe and layout-v2 GEMM2 kernels.
"""AOT pre-compile for the FlyDSL MXMOE a4w4/a8w4 port (GEMM1 / GEMM2) and the
layout-v2 GEMM2 kernels.

Parses flydsl_mxmoe_* and flydsl_moe2_layout_* rows from the existing model
configs plus the active FMoE CSV, and warms the FlyDSL disk cache via the same
Expand All @@ -25,9 +26,12 @@
# moe.py defers every ``flydsl_moe2_layout_`` name to this module, so a CSV the
# glob misses gets no AOT job at all and JITs on the first inference call.
DEFAULT_CSVS = sorted(
set(glob.glob(f"{_MODEL_CONFIG_DIR}/*_fp4_tuned_fmoe.csv"))
| set(glob.glob(f"{_MODEL_CONFIG_DIR}/*_a4w4_tuned_fmoe.csv"))
| set(glob.glob(f"{_MODEL_CONFIG_DIR}/*_a8w4_tuned_fmoe.csv"))
set(
glob.glob(f"{_MODEL_CONFIG_DIR}/*_fp4_tuned_fmoe.csv")
+ glob.glob(f"{_MODEL_CONFIG_DIR}/*_fp8fp4_tuned_fmoe.csv")
+ glob.glob(f"{_MODEL_CONFIG_DIR}/*_a4w4_tuned_fmoe.csv")
+ glob.glob(f"{_MODEL_CONFIG_DIR}/*_a8w4_tuned_fmoe.csv")
)
)
_ACTIVE_FMOE_CSV = AITER_CONFIGS.AITER_CONFIG_FMOE_FILE
if os.path.exists(_ACTIVE_FMOE_CSV) and _ACTIVE_FMOE_CSV not in DEFAULT_CSVS:
Expand Down Expand Up @@ -67,13 +71,27 @@ def _job_key(job: dict) -> tuple:
return (
1,
job["BM"],
job["BN"],
job["BK"],
job["use_nt"],
job["inline_quant"],
job["prefetch_hidden"],
job["D_HIDDEN"],
job["D_INTER"],
job["NE"],
job["topk"],
job["xcd_swizzle"],
job["a_dtype"],
job["out_dtype"],
job["act"],
job["situ_beta"],
job["situ_linear_beta"],
job["swiglu_limit"],
job["enable_bias"],
job["interleave"],
job["native_scale_layout"],
job["num_waves"],
job["k_wave"],
)
return (
2,
Expand All @@ -89,12 +107,17 @@ def _job_key(job: dict) -> tuple:


def parse_csv(csv_path: str):
"""Parse an fp4 tuned CSV into unique mxmoe-port compile jobs (one per stage)."""
"""Parse a tuned CSV into unique MXMOE-port compile jobs (one per stage)."""
from aiter.ops.flydsl.moe_common import (
DEFAULT_SITUV2_BETA,
DEFAULT_SITUV2_LINEAR_BETA,
)
from aiter.ops.flydsl.mxfp4_gemm2_kernels import _epilog_of
from aiter.ops.flydsl.mxfp4_kname import (
_is_mxfp4_kname,
_parse_mxfp4_g1_kname,
_parse_mxfp4_g2_kname,
native_scale_layout_for,
parse_flydsl_v2_gemm2_kernel,
)

Expand All @@ -110,13 +133,15 @@ def _add(job):

with open(csv_path, newline="") as f:
for row in csv.DictReader(f):
token = int(row["token"])
topk = int(row["topk"])
# Shape comes from CSV columns; v2 GEMM2 aligns K to its encoded BK.
model_dim = int(row["model_dim"])
expert = int(row["expert"])
inter_dim = int(row["inter_dim"])
d_inter = ((inter_dim + 255) // 256) * 256
d_inter_real = inter_dim if inter_dim != d_inter else None

kn1 = (row.get("kernelName1") or "").strip()
kn2 = (row.get("kernelName2") or "").strip()
v2_g2 = parse_flydsl_v2_gemm2_kernel(kn2)
if v2_g2 is not None:
Expand All @@ -127,23 +152,54 @@ def _add(job):
v2_d_inter = d_inter
v2_d_inter_real = d_inter_real

kn1 = (row.get("kernelName1") or "").strip()
if _is_mxfp4_kname(kn1):
p1 = _parse_mxfp4_g1_kname(kn1)
_add(
{
"stage": 1,
"kernel_name": kn1,
"BM": p1["BM"],
"use_nt": p1["use_nt"],
"inline_quant": p1["inline_quant"],
"D_HIDDEN": model_dim,
"D_INTER": v2_d_inter,
"NE": expert,
"topk": topk,
"xcd_swizzle": p1["xcd_swizzle"],
}
)
situ_params = [(1.0, 1.0)]
if p1["act"] == "situv2":
situ_params.append(
(DEFAULT_SITUV2_BETA, DEFAULT_SITUV2_LINEAR_BETA)
)
for situ_beta, situ_linear_beta in situ_params:
_add(
{
"stage": 1,
"kernel_name": kn1,
"BM": p1["BM"],
"BN": p1["BN"],
"BK": p1["BK"],
"use_nt": p1["use_nt"],
"n_tokens": token,
"inline_quant": p1["inline_quant"],
"prefetch_hidden": p1.get("prefetch_hidden", False),
"D_HIDDEN": model_dim,
# Runtime derives D_INTER from the *stored* weight
# width (``w1.shape[1] // 2``), and non-aligned
# shards ship padded to a multiple of 256 with the
# logical width carried separately in
# ``w2.inter_real`` -- the same convention
# ``is_mxfp4_moe_shape_supported`` uses. Keying on
# the raw CSV ``inter_dim`` would miss those rows
# (Kimi-K3: 384 stored as 512). ``d_inter`` is used
# rather than the GEMM2 ``v2_d_inter`` because the
# latter pads to a backend-specific tile_k.
"D_INTER": d_inter,
"NE": expert,
"topk": topk,
"xcd_swizzle": p1["xcd_swizzle"],
"a_dtype": p1["a_dtype"],
"out_dtype": p1["out_dtype"],
"act": p1["act"],
"situ_beta": situ_beta,
"situ_linear_beta": situ_linear_beta,
"swiglu_limit": 7.0,
"enable_bias": p1["enable_bias"],
"interleave": p1["interleave"],
"native_scale_layout": native_scale_layout_for(p1["BM"]),
"num_waves": p1.get("num_waves", 4),
"k_wave": p1.get("k_wave", 1),
}
)

if v2_g2 is not None:
bm = v2_g2["tile_m"]
inter_dim_pad = v2_d_inter - inter_dim
Expand Down Expand Up @@ -185,8 +241,6 @@ def _add(job):
"has_pad": inter_dim_pad > 0 or model_dim_pad > 0,
"out_dtype": out_dtype,
"enable_bias": enable_bias,
# In the compiled kernel tag: must match the runtime
# wrapper or the AOT entry is keyed differently.
"g2_spart": v2_g2["spart"],
"g2_bf16_lds": v2_g2["bf16_lds"],
}
Expand Down Expand Up @@ -248,15 +302,29 @@ def _compile_stage1(job):
inter_sorted_quant=d,
inter_sorted_shuffled_scale=d,
hidden_states=d,
n_tokens=job["BM"],
n_tokens=job["n_tokens"],
BM=job["BM"],
BN=job["BN"],
BK=job["BK"],
use_nt=job["use_nt"],
inline_quant=job["inline_quant"],
prefetch_hidden=job["prefetch_hidden"],
NE=job["NE"],
D_HIDDEN=job["D_HIDDEN"],
D_INTER=job["D_INTER"],
topk=job["topk"],
xcd_swizzle=job["xcd_swizzle"],
a_dtype=job["a_dtype"],
out_dtype=job["out_dtype"],
act=job["act"],
situ_beta=job["situ_beta"],
situ_linear_beta=job["situ_linear_beta"],
swiglu_limit=job["swiglu_limit"],
bias=d if job["enable_bias"] else None,
interleave=job["interleave"],
native_scale_layout=job["native_scale_layout"],
num_waves=job["num_waves"],
k_wave=job["k_wave"],
stream=0,
)

Expand Down Expand Up @@ -371,6 +439,7 @@ def _compile_v2_stage2(job):
job["BM"],
job["topk"],
job["N_OUT"],
model_dim_pad=job["model_dim_pad"],
expert_mask=None,
topk_ids=None,
stream=0,
Expand Down Expand Up @@ -418,7 +487,8 @@ def main():
type=str,
nargs="+",
default=DEFAULT_CSVS,
help="Path(s) to tuned FMoE CSVs; default: existing model configs plus active merged FMoE config",
help="Path(s) to tuned FMoE CSVs; default: fp4, fp8fp4, a4w4, and a8w4 "
"model configs plus the active merged FMoE config",
)
args = parser.parse_args()

Expand All @@ -436,7 +506,7 @@ def main():
stage2_jobs = [j for j in all_jobs if j["stage"] == 2]

print("=" * 72)
print("FlyDSL mxmoe a4w4 MoE-port AOT Pre-compilation")
print("FlyDSL MXMOE a4w4/a8w4 AOT Pre-compilation")
print("=" * 72)
for csv_path in csv_paths:
print(f" CSV: {csv_path}")
Expand Down
10 changes: 5 additions & 5 deletions aiter/configs/model_configs/glm5_fp4_tuned_fmoe.csv
Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,9 @@ gfx950,256,8192,6144,1024,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_
gfx950,256,16384,6144,1024,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,64,0,1083.8484,flydsl_moe1_afp4_wfp4_bf16_t64x128x256_w2_bnt0_fp4,0.9%,1206.3064,flydsl_moe2_layout_afp4_wfp4_bf16_t64x256x128_reduce_sbm64,1.2%,2290.1548,0,0,0,2430.52,2249.94,
gfx950,256,32768,6144,1024,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,1996.7999,flydsl_moe1_afp4_wfp4_bf16_t128x128x256_w4_bnt0_fp4,0.9%,2417.8726,flydsl_moe2_layout_afp4_wfp4_bf16_t64x256x128_reduce_sbm128,1.2%,4414.6725,0,0,0,2521.72,1235.58,
gfx950,256,1,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,32,0,11.5491,flydsl_moe1_afp4_wfp4_bf16_t32x32x256_w4_kw4_fp4,1.0%,7.3233,flydsl_moe2_layout_afp4_wfp4_bf16_t32x128x128_atomic_sbm32,1.3%,18.8724,0,0,0,9.0,128514.38,
gfx950,256,2,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,28.7583,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.012391,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x256_atomic_sbm16,0.012391,28.7583,0,0,0,0.0,0.0,
gfx950,256,4,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,35.5442,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.012156,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x256_atomic_nt_sbm16,0.012156,35.5442,0,0,0,0.0,0.0,
gfx950,256,8,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,68.1308,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.012034,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x256_atomic_sbm16,0.012034,68.1308,0,0,0,0.0,0.0,
gfx950,256,2,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,16.3995,flydsl_mxmoe_g1_a4w4_16x128x256_f16in_nt,1.2%,5.622,flydsl_mxmoe_g2_a4w4_16x256x256_atomic,0.0%,22.0215,0,0,0,15.43,110137.51,
gfx950,256,4,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,23.1407,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,1.2%,10.9459,flydsl_mxmoe_g2_a4w4_16x256x256_atomic,0.0%,34.0866,0,0,0,19.93,71154.94,
gfx950,256,8,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,42.5523,flydsl_mxmoe_g1_a4w4_16x128x256_f16in_nt_xcd2,1.2%,17.0413,flydsl_mxmoe_g2_a4w4_16x256x256_atomic,0.0%,59.5936,0,0,0,22.8,40700.74,
gfx950,256,16,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,91.5029,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.011945,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x256_atomic_sbm16,0.011945,91.5029,0,0,0,0.0,0.0,
gfx950,256,32,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,135.3655,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.011955,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x256_atomic_nt_sbm16,0.011955,135.3655,0,0,0,0.0,0.0,
gfx950,256,64,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,181.4689,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.011692,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x128x128_atomic_nt_sbm16,0.011692,181.4689,0,0,0,0.0,0.0,
Expand All @@ -45,8 +45,8 @@ gfx950,256,1024,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e
gfx950,256,2048,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,181.274,flydsl_moe1_afp4_wfp4_bf16_t128x128x256_w2_fp4,0.9%,185.3303,flydsl_moe2_layout_afp4_wfp4_bf16_t64x256x128_reduce_persist_sbm128,1.2%,366.6043,0,0,0,948.96,6718.7,
gfx950,256,4096,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,64,0,251.6512,flydsl_moe1_afp4_wfp4_bf16_t64x128x256_w3_bnt0_xcd4_fp4,0.9%,289.1168,flydsl_moe2_layout_afp4_wfp4_bf16_t64x256x128_reduce_persist_sbm64,1.2%,540.768,0,0,0,1286.66,4624.63,
gfx950,256,8192,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,64,0,361.1843,flydsl_moe1_afp4_wfp4_bf16_t64x128x256_w4_bnt0_fp4,0.9%,519.3092,flydsl_moe2_layout_afp4_wfp4_bf16_t64x256x256_reduce_sbm64,1.2%,880.4935,0,0,0,1580.44,2926.03,
gfx950,256,16384,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,1625.8568,flydsl_mxmoe_g1_a4w4_128x256x256,0.011729,0.0,flydsl_mxmoe_g2_a4w4_128x256x256_f4out,0.011729,1625.8568,0,0,0,0.0,0.0,
gfx950,256,32768,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,2997.8444,flydsl_mxmoe_g1_a4w4_128x256x256,0.011733,0.0,flydsl_mxmoe_g2_a4w4_128x256x256_f4out,0.011733,2997.8444,0,0,0,0.0,0.0,
gfx950,256,16384,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,504.2785,flydsl_mxmoe_g1_a4w4_128x256x256_xcd2,1.2%,573.7599,flydsl_mxmoe_g2_a4w4_128x256x256_f4out,0.0%,1078.0384,0,0,0,2581.67,2529.92,
gfx950,256,32768,6144,512,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,128,0,938.3141,flydsl_mxmoe_g1_a4w4_128x256x256_xcd2,1.2%,1117.0695,flydsl_mxmoe_g2_a4w4_128x256x256,0.0%,2055.3836,0,0,0,2708.15,1473.85,
gfx950,256,1,6144,256,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,32,0,10.4289,flydsl_moe1_afp4_wfp4_bf16_t32x32x256_kw4_fp4,0.9%,6.2885,flydsl_moe2_layout_afp4_wfp4_bf16_t32x128x256_atomic_nt_sbm32,1.3%,16.7174,0,0,0,5.08,72540.98,
gfx950,256,2,6144,256,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,32,0,11.2231,flydsl_moe1_afp4_wfp4_bf16_t32x32x256_w2_bnt0_kw4_fp4,0.9%,7.6731,flydsl_moe2_layout_afp4_wfp4_bf16_t32x256x128_atomic_nt_sbm32,1.2%,18.8962,0,0,0,8.99,64177.72,
gfx950,256,4,6144,256,257,9,ActivationType.Silu,torch.bfloat16,torch.float4_e2m1fn_x2,torch.float4_e2m1fn_x2,QuantType.per_1x32,1,0,16,0,29.5482,flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt,0.012428,0.0,flydsl_moe2_layout_afp4_wfp4_bf16_t16x256x256_atomic_sbm16,0.012428,29.5482,0,0,0,0.0,0.0,
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