Skip to content

[WaveTransform] Fix some AMDGPU intrinsic tests #2703

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
cdevadas wants to merge 1 commit into
base: amd-feature/wave-transform
Choose a base branch
from
Open

[WaveTransform] Fix some AMDGPU intrinsic tests #2703

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 24 additions & 10 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.whole.wave-w64.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -amdgpu-late-wave-transform=0 -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL12 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL12 %s
; RUN: llc -amdgpu-late-wave-transform=1 -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL12 %s
; RUN: llc -amdgpu-late-wave-transform=0 -global-isel=1 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=GISEL10 %s
; RUN: llc -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL10 %s
; RUN: llc -amdgpu-late-wave-transform=1 -global-isel=0 -O2 -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 < %s | FileCheck --check-prefix=DAGISEL10 %s

; This shouldn't be too different from wave32, so we'll only test one case.

Expand Down Expand Up @@ -50,14 +50,21 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL12-NEXT: s_wait_samplecnt 0x0
; DAGISEL12-NEXT: s_wait_bvhcnt 0x0
; DAGISEL12-NEXT: s_wait_kmcnt 0x0
; DAGISEL12-NEXT: s_or_saveexec_b64 s[10:11], -1
; DAGISEL12-NEXT: s_or_saveexec_b64 s[8:9], -1
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[8:9]
; DAGISEL12-NEXT: s_mov_b32 s7, s6
; DAGISEL12-NEXT: s_mov_b32 s6, s5
; DAGISEL12-NEXT: s_mov_b32 s5, s4
; DAGISEL12-NEXT: s_mov_b32 s4, s3
; DAGISEL12-NEXT: v_cmp_ne_u32_e32 vcc, 1, v1
; DAGISEL12-NEXT: s_xor_b64 s[10:11], vcc, exec
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; DAGISEL12-NEXT: ; %bb.1: ; %shader
; DAGISEL12-NEXT: s_xor_b64 s[8:9], exec, s[10:11]
; DAGISEL12-NEXT: s_mov_b64 exec, s[10:11]
; DAGISEL12-NEXT: ; divergent control-flow edge
; DAGISEL12-NEXT: s_cbranch_execz .LBB0_2
; DAGISEL12-NEXT: .LBB0_1: ; %shader
; DAGISEL12-NEXT: s_or_saveexec_b64 s[10:11], -1
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
Expand All @@ -67,7 +74,8 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL12-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL12-NEXT: v_add_nc_u32_e32 v10, 42, v13
; DAGISEL12-NEXT: v_mov_b32_e32 v12, s13
; DAGISEL12-NEXT: ; %bb.2: ; %tail
; DAGISEL12-NEXT: .LBB0_2: ; %tail
; DAGISEL12-NEXT: s_wait_alu depctr_sa_sdst(0)
; DAGISEL12-NEXT: s_or_b64 exec, exec, s[8:9]
; DAGISEL12-NEXT: s_mov_b64 exec, s[6:7]
; DAGISEL12-NEXT: s_setpc_b64 s[4:5]
Expand Down Expand Up @@ -100,21 +108,27 @@ define amdgpu_cs_chain void @basic(<3 x i32> inreg %sgpr, ptr inreg %callee, i64
; DAGISEL10-LABEL: basic:
; DAGISEL10: ; %bb.0: ; %entry
; DAGISEL10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; DAGISEL10-NEXT: s_or_saveexec_b64 s[10:11], -1
; DAGISEL10-NEXT: s_or_saveexec_b64 s[8:9], -1
; DAGISEL10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[8:9]
; DAGISEL10-NEXT: s_mov_b32 s7, s6
; DAGISEL10-NEXT: s_mov_b32 s6, s5
; DAGISEL10-NEXT: s_mov_b32 s5, s4
; DAGISEL10-NEXT: s_mov_b32 s4, s3
; DAGISEL10-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
; DAGISEL10-NEXT: ; %bb.1: ; %shader
; DAGISEL10-NEXT: v_cmp_ne_u32_e32 vcc, 1, v1
; DAGISEL10-NEXT: s_xor_b64 s[10:11], vcc, exec
; DAGISEL10-NEXT: s_xor_b64 s[8:9], exec, s[10:11]
; DAGISEL10-NEXT: s_mov_b64 exec, s[10:11]
; DAGISEL10-NEXT: ; divergent control-flow edge
; DAGISEL10-NEXT: s_cbranch_execz .LBB0_2
; DAGISEL10-NEXT: .LBB0_1: ; %shader
; DAGISEL10-NEXT: s_or_saveexec_b64 s[10:11], -1
; DAGISEL10-NEXT: v_cndmask_b32_e64 v0, 0x47, v13, s[10:11]
; DAGISEL10-NEXT: v_cmp_ne_u32_e64 s[12:13], 0, v0
; DAGISEL10-NEXT: s_mov_b64 exec, s[10:11]
; DAGISEL10-NEXT: v_mov_b32_e32 v11, s12
; DAGISEL10-NEXT: v_add_nc_u32_e32 v10, 42, v13
; DAGISEL10-NEXT: v_mov_b32_e32 v12, s13
; DAGISEL10-NEXT: ; %bb.2: ; %tail
; DAGISEL10-NEXT: .LBB0_2: ; %tail
; DAGISEL10-NEXT: s_or_b64 exec, exec, s[8:9]
; DAGISEL10-NEXT: s_mov_b64 exec, s[6:7]
; DAGISEL10-NEXT: s_setpc_b64 s[4:5]
Expand Down
35 changes: 22 additions & 13 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.inverse.ballot.i64.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -amdgpu-late-wave-transform=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL_W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W64 %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize64 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W64 %s
; RUN: llc -amdgpu-late-wave-transform=0 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GISEL_W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W32 %s
; RUN: llc -amdgpu-late-wave-transform=1 -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -mattr=+wavefrontsize32 -global-isel=0 < %s | FileCheck -check-prefix=SDAG_W32 %s

declare i1 @llvm.amdgcn.inverse.ballot.i64(i64)

Expand Down Expand Up @@ -190,10 +190,9 @@ define amdgpu_cs void @sgpr_inverse_ballot(i64 inreg %input, ptr addrspace(1) %o
;
; SDAG_W64-LABEL: sgpr_inverse_ballot:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_mov_b32 s2, 0
; SDAG_W64-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; SDAG_W64-NEXT: s_mov_b32 s0, 0
; SDAG_W64-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s0
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s2
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
;
Expand Down Expand Up @@ -311,16 +310,21 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
;
; SDAG_W64-LABEL: inverse_ballot_branch:
; SDAG_W64: ; %bb.0: ; %entry
; SDAG_W64-NEXT: s_and_b64 s[4:5], exec, s[2:3]
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: s_xor_b64 s[2:3], s[2:3], -1
; SDAG_W64-NEXT: v_mov_b32_e32 v2, s0
; SDAG_W64-NEXT: s_xor_b64 s[4:5], s[2:3], -1
; SDAG_W64-NEXT: s_and_saveexec_b64 s[2:3], s[4:5]
; SDAG_W64-NEXT: ; %bb.1: ; %if
; SDAG_W64-NEXT: s_and_b64 s[4:5], s[2:3], exec
; SDAG_W64-NEXT: s_xor_b64 s[2:3], exec, s[4:5]
; SDAG_W64-NEXT: s_mov_b64 exec, s[4:5]
; SDAG_W64-NEXT: ; divergent control-flow edge
; SDAG_W64-NEXT: s_cbranch_execz .LBB6_2
; SDAG_W64-NEXT: .LBB6_1: ; %if
; SDAG_W64-NEXT: s_add_u32 s0, s0, 1
; SDAG_W64-NEXT: s_addc_u32 s1, s1, 0
; SDAG_W64-NEXT: v_mov_b32_e32 v3, s1
; SDAG_W64-NEXT: v_mov_b32_e32 v2, s0
; SDAG_W64-NEXT: ; %bb.2: ; %endif
; SDAG_W64-NEXT: .LBB6_2: ; %endif
; SDAG_W64-NEXT: s_or_b64 exec, exec, s[2:3]
; SDAG_W64-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W64-NEXT: s_endpgm
Expand All @@ -342,14 +346,19 @@ define amdgpu_cs void @inverse_ballot_branch(i64 inreg %s0_1, i64 inreg %s2, ptr
;
; SDAG_W32-LABEL: inverse_ballot_branch:
; SDAG_W32: ; %bb.0: ; %entry
; SDAG_W32-NEXT: s_and_b32 s3, exec_lo, s2
; SDAG_W32-NEXT: s_xor_b32 s2, s2, -1
; SDAG_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; SDAG_W32-NEXT: s_xor_b32 s3, s2, -1
; SDAG_W32-NEXT: s_and_saveexec_b32 s2, s3
; SDAG_W32-NEXT: ; %bb.1: ; %if
; SDAG_W32-NEXT: s_and_b32 s3, s2, exec_lo
; SDAG_W32-NEXT: s_xor_b32 s2, exec_lo, s3
; SDAG_W32-NEXT: s_mov_b32 exec_lo, s3
; SDAG_W32-NEXT: ; divergent control-flow edge
; SDAG_W32-NEXT: s_cbranch_execz .LBB6_2
; SDAG_W32-NEXT: .LBB6_1: ; %if
; SDAG_W32-NEXT: s_add_u32 s0, s0, 1
; SDAG_W32-NEXT: s_addc_u32 s1, s1, 0
; SDAG_W32-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; SDAG_W32-NEXT: ; %bb.2: ; %endif
; SDAG_W32-NEXT: .LBB6_2: ; %endif
; SDAG_W32-NEXT: s_or_b32 exec_lo, exec_lo, s2
; SDAG_W32-NEXT: global_store_b64 v[0:1], v[2:3], off
; SDAG_W32-NEXT: s_endpgm
Expand Down
Loading