Discussion on methods of instantiating customized AFUs

There are several ways to instantiate a customized AFU to be used with the provided FIM, which is a static design and poses a standard interface for the AFU to be connected.

The most generic way is instantiating the AFU as a HDL sub-module inside the HDL-wrapper provided by the FIM. This is truly Vendor-Neutral and can be applied to the design flow of both Xilinx and Intel.

A vendor specific way is to design the AFU as an IP, and instantiate it using the IP integration tool, such as IPI from Xilinx and Qsys from Intel.

When targeting Xilinx devices, a Block Design template is provided in ./hw/src/ipi/afu_customer.bd.tcl. This template is a partial AFU design and requires user IP to be added and connected. Just follow the README in ./hw/prj/afu/ to use this partial design as a base and add a user designed IP, such as that provided in ./hw/src/afu_customize/hls_ip/adder_axilite/. Hand-written HDL files can also be added as a Block Design IP and connected with this base design.