Skip to content

Upgrade to the upcoming version of avr-device #656

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 6 commits into
base: main
Choose a base branch
from
Open

Upgrade to the upcoming version of avr-device #656

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
4684411
[NO MERGE] Temporarily use git version of avr-device
Rahix May 4, 2024
eb7ba7b
[NO MERGE] ci: Temporarily disable fail-fast
Rahix Nov 4, 2024
edf6480
treewide: Apply changes for new svd2rust API
Rahix May 4, 2024
da4681c
treewide: Remove critical-section-impl crate features
Rahix Apr 30, 2025
ddfe35b
generic: Accommodate for new return value of write() and modify()
Rahix Apr 29, 2025
3e05785
examples: nano168: Fix wrong interrupt annotation
Rahix Apr 30, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion .github/workflows/ci.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ jobs:
ci:
name: "${{ matrix.m.type }}: ${{ matrix.m.name }}"
strategy:
fail-fast: true
fail-fast: false
matrix:
m:
- type: board
Expand Down
3 changes: 3 additions & 0 deletions Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,3 +42,6 @@ exclude = [
"ravedude",
]
resolver = "2"

[patch.crates-io]
avr-device = { git = "https://github.com/rahix/avr-device", rev = "330cdf1fb1a7301b9d6cf62491c16e69d6aa7312" }
2 changes: 0 additions & 2 deletions arduino-hal/Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,6 @@ categories = ["no-std", "embedded", "hardware-support"]
default = ["rt"]
rt = ["avr-device/rt"]

critical-section-impl = ["avr-device/critical-section-impl"]

board-selected = []
mcu-atmega = []
mcu-attiny = []
Expand Down
10 changes: 5 additions & 5 deletions avr-hal-generic/src/adc.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -250,17 +250,17 @@ macro_rules! impl_adc {

#[inline]
fn raw_read_adc(&self) -> u16 {
self.adc.read().bits()
self.adc().read().bits()
}

#[inline]
fn raw_is_converting(&self) -> bool {
self.adcsra.read().adsc().bit_is_set()
self.adcsra().read().adsc().bit_is_set()
}

#[inline]
fn raw_start_conversion(&mut self) {
self.adcsra.modify(|_, w| w.adsc().set_bit());
self.adcsra().modify(|_, w| w.adsc().set_bit());
}

#[inline]
Expand All @@ -276,7 +276,7 @@ macro_rules! impl_adc {
match channel {
$(
x if x == $pin_channel => {
$(self.$didr.modify(|_, w| w.$didr_method().set_bit());)?
$(self.$didr().modify(|_, w| w.$didr_method().set_bit());)?
}
)+
_ => unreachable!(),
Expand All @@ -288,7 +288,7 @@ macro_rules! impl_adc {
match channel {
$(
x if x == $pin_channel => {
$(self.$didr.modify(|_, w| w.$didr_method().clear_bit());)?
$(self.$didr().modify(|_, w| w.$didr_method().clear_bit());)?
}
)+
_ => unreachable!(),
Expand Down
51 changes: 26 additions & 25 deletions avr-hal-generic/src/eeprom.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -159,8 +159,8 @@ macro_rules! impl_eeprom_common {
$set_address
}

self.eecr.write(|w| w.eere().set_bit());
self.eedr.read().bits()
self.eecr().write(|w| w.eere().set_bit());
self.eedr().read().bits()
}
}

Expand All @@ -173,8 +173,8 @@ macro_rules! impl_eeprom_common {
}

//Start EEPROM read operation
self.eecr.write(|w| w.eere().set_bit());
let old_value = self.eedr.read().bits();
self.eecr().write(|w| w.eere().set_bit());
let old_value = self.eedr().read().bits();
let diff_mask = old_value ^ data;

// Check if any bits are changed to '1' in the new value.
Expand All @@ -184,33 +184,33 @@ macro_rules! impl_eeprom_common {
// Check if any bits in the new value are '0'.
if data != 0xff {
// Now we know that some bits need to be programmed to '0' also.
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.

{
let $periph_ewmode_var = &self;
$set_erasewrite_mode
}
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
} else {
// Now we know that all bits should be erased.
{
let $periph_emode_var = &self;
$set_erase_mode
}
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
}
}
//Now we know that _no_ bits need to be erased to '1'.
else {
// Check if any bits are changed from '1' in the old value.
if diff_mask != 0 {
// Now we know that _some_ bits need to the programmed to '0'.
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
{
let $periph_wmode_var = &self;
$set_write_mode
}
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
}
}
}
Expand All @@ -229,7 +229,7 @@ macro_rules! impl_eeprom_common {
$set_erase_mode
}
// Start Erase-only operation.
self.eecr.modify(|_, w| w.eepe().set_bit());
self.eecr().modify(|_, w| w.eepe().set_bit());
}
}
}
Expand All @@ -249,7 +249,7 @@ macro_rules! impl_eeprom_atmega_old {
#[inline]
pub unsafe fn wait_read(regs: &$EEPROM) {
//Wait for completion of previous write.
while regs.eecr.read().eewe().bit_is_set() {}
while regs.eecr().read().eewe().bit_is_set() {}
}

#[inline]
Expand All @@ -268,8 +268,8 @@ macro_rules! impl_eeprom_atmega_old {
unsafe {
atmega_helper::set_address(&self, address);
}
self.eecr.write(|w| w.eere().set_bit());
self.eedr.read().bits()
self.eecr().write(|w| w.eere().set_bit());
self.eedr().read().bits()
}

fn raw_write_byte(&mut self, address: u16, data: u8) {
Expand All @@ -278,11 +278,12 @@ macro_rules! impl_eeprom_atmega_old {
}

//Start EEPROM read operation
self.eedr.write(|w| unsafe { w.bits(data) });
self.eedr().write(|w| unsafe { w.bits(data) });

self.eecr.write(|w| w.eemwe().set_bit().eewe().clear_bit());
self.eecr()
.write(|w| w.eemwe().set_bit().eewe().clear_bit());

self.eecr.write(|w| w.eewe().set_bit());
self.eecr().write(|w| w.eewe().set_bit());
}

fn raw_erase_byte(&mut self, address: u16) {
Expand All @@ -305,7 +306,7 @@ macro_rules! impl_eeprom_atmega {
#[inline]
pub unsafe fn wait_read(regs: &$EEPROM) {
//Wait for completion of previous write.
while regs.eecr.read().eepe().bit_is_set() {}
while regs.eecr().read().eepe().bit_is_set() {}
}
#[inline]
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
Expand All @@ -316,21 +317,21 @@ macro_rules! impl_eeprom_atmega {
}
#[inline]
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit, and and Erase+Write mode mode..
w.eempe().set_bit().eepm().val_0x00()
})
});
}
#[inline]
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit, and Erase-only mode..
w.eempe().set_bit().eepm().val_0x01()
});
}
#[inline]
pub unsafe fn set_write_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit, and Write-only mode..
w.eempe().set_bit().eepm().val_0x02()
});
Expand Down Expand Up @@ -362,7 +363,7 @@ macro_rules! impl_eeprom_attiny {
mod attiny_helper {
#[inline]
pub unsafe fn wait_read(regs: &$EEPROM) {
while regs.eecr.read().eepe().bit_is_set() {}
while regs.eecr().read().eepe().bit_is_set() {}
}
#[inline]
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
Expand All @@ -373,21 +374,21 @@ macro_rules! impl_eeprom_attiny {
}
#[inline]
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit...and and Erase+Write mode mode..
w.eempe().set_bit().eepm().atomic()
});
}
#[inline]
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit, and Erase-only mode..
w.eempe().set_bit().eepm().erase()
});
}
#[inline]
pub unsafe fn set_write_mode(regs: &$EEPROM) {
regs.eecr.write(|w| {
regs.eecr().write(|w| {
// Set Master Write Enable bit, and Write-only mode..
w.eempe().set_bit().eepm().write()
});
Expand Down
40 changes: 20 additions & 20 deletions avr-hal-generic/src/i2c.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -466,22 +466,22 @@ macro_rules! impl_i2c_twi {
fn raw_setup<CLOCK: $crate::clock::Clock>(&mut self, speed: u32) {
// Calculate TWBR register value
let twbr = ((CLOCK::FREQ / speed) - 16) / 2;
self.twbr.write(|w| unsafe { w.bits(twbr as u8) });
self.twbr().write(|w| unsafe { w.bits(twbr as u8) });

// Disable prescaler
self.twsr.write(|w| w.twps().prescaler_1());
self.twsr().write(|w| w.twps().prescaler_1());
}

#[inline]
fn raw_start(&mut self, address: u8, direction: Direction) -> Result<(), Error> {
// Write start condition
self.twcr
self.twcr()
.write(|w| w.twen().set_bit().twint().set_bit().twsta().set_bit());
// wait()
while self.twcr.read().twint().bit_is_clear() {}
while self.twcr().read().twint().bit_is_clear() {}

// Validate status
match self.twsr.read().tws().bits() {
match self.twsr().read().tws().bits() {
$crate::i2c::twi_status::TW_START | $crate::i2c::twi_status::TW_REP_START => (),
$crate::i2c::twi_status::TW_MT_ARB_LOST
| $crate::i2c::twi_status::TW_MR_ARB_LOST => {
Expand All @@ -502,13 +502,13 @@ macro_rules! impl_i2c_twi {
0
};
let rawaddr = (address << 1) | dirbit;
self.twdr.write(|w| unsafe { w.bits(rawaddr) });
self.twdr().write(|w| unsafe { w.bits(rawaddr) });
// transact()
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
while self.twcr.read().twint().bit_is_clear() {}
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
while self.twcr().read().twint().bit_is_clear() {}

// Check if the slave responded
match self.twsr.read().tws().bits() {
match self.twsr().read().tws().bits() {
$crate::i2c::twi_status::TW_MT_SLA_ACK
| $crate::i2c::twi_status::TW_MR_SLA_ACK => (),
$crate::i2c::twi_status::TW_MT_SLA_NACK
Expand All @@ -535,12 +535,12 @@ macro_rules! impl_i2c_twi {
#[inline]
fn raw_write(&mut self, bytes: &[u8]) -> Result<(), Error> {
for byte in bytes {
self.twdr.write(|w| unsafe { w.bits(*byte) });
self.twdr().write(|w| unsafe { w.bits(*byte) });
// transact()
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
while self.twcr.read().twint().bit_is_clear() {}
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
while self.twcr().read().twint().bit_is_clear() {}

match self.twsr.read().tws().bits() {
match self.twsr().read().tws().bits() {
$crate::i2c::twi_status::TW_MT_DATA_ACK => (),
$crate::i2c::twi_status::TW_MT_DATA_NACK => {
self.raw_stop()?;
Expand All @@ -565,17 +565,17 @@ macro_rules! impl_i2c_twi {
let last = buffer.len() - 1;
for (i, byte) in buffer.iter_mut().enumerate() {
if i != last {
self.twcr
self.twcr()
.write(|w| w.twint().set_bit().twen().set_bit().twea().set_bit());
// wait()
while self.twcr.read().twint().bit_is_clear() {}
while self.twcr().read().twint().bit_is_clear() {}
} else {
self.twcr.write(|w| w.twint().set_bit().twen().set_bit());
self.twcr().write(|w| w.twint().set_bit().twen().set_bit());
// wait()
while self.twcr.read().twint().bit_is_clear() {}
while self.twcr().read().twint().bit_is_clear() {}
}

match self.twsr.read().tws().bits() {
match self.twsr().read().tws().bits() {
$crate::i2c::twi_status::TW_MR_DATA_ACK
| $crate::i2c::twi_status::TW_MR_DATA_NACK => (),
$crate::i2c::twi_status::TW_MR_ARB_LOST => {
Expand All @@ -589,14 +589,14 @@ macro_rules! impl_i2c_twi {
}
}

*byte = self.twdr.read().bits();
*byte = self.twdr().read().bits();
}
Ok(())
}

#[inline]
fn raw_stop(&mut self) -> Result<(), Error> {
self.twcr
self.twcr()
.write(|w| w.twen().set_bit().twint().set_bit().twsto().set_bit());
Ok(())
}
Expand Down
Loading