This brief article is about the electronic design of system-on-chips (SOC) including FPGAs and ARM-Processors.
In the Zynq 7000 Embedded Design Tutorial (UG1165) AMD (Xilinx) shares the example 6 "Using the GP Port in Zynq Devices" plus the SW-code hello_pl.c in the corresponding GitHub-repository targeting the AMD ZC702 rev 1.0 evaluation board. The AXI-GPIO, AXI-timer, interrupt and the EMIO-interface are covered therein.
The original code does not work right out-of-the-box in the context of the environment described below. Hence, a modified C-code and an instruction is presented.
| Item | Version |
|---|---|
| UG1165 document | 2025-07-29, 2025.1 |
| Vivado | 2025.1 |
| Vitis | 2025.1 Unified |
| .. installed on OS | Ubuntu 24.04.03 LTS |
| HW-platform | ZedBoard Rev. F |
- Follow the tutorial UG1165 with the following exceptions ...
- Section "Assigning Location Constraints to External Pins" of UG1165 -> In the case of the Zedboard consider:
- SW5 and SW7 may be connected to the slide-switches SW5 (PACKAGE_PIN H18) and SW7 (M15), accordingly, in order to keep the names.
- .. those Pins are connected to Bank 35, which refer to 1.8V (and not to 2.5V). Consider this in the settings of the I/O ports. Instead of engaging "IO Planning" in Vivado the adaption of the genuine constrains-file Zedboard-Master.xdc was preferred here (via "Add Sources -> Add or create constraints"). The later is shared in this repository for your information.
- Section "Testing the PL IP with Prepared Software" of UG1165:
- The creation of the corresponding application component in Vitis is working easily going the route Examples > Embedded Software Examples > Hello World > ..
- Pick the file helloworld.c shared in this repository (instead of hello_pl.c by AMD). Copy-and-paste its content into the (cleared) Hello World example.
- Build and run your program.
- The design has been tested for the SDT-case as used by Vitis Unified. The non-SDT-case as used by Vitis Classic is not tested at all.
- The name of the LED was left to be "DS23" for simplicity despite it is called LD9 on the ZedBoard.
- The frequency of FCLK_CLK0 is 100 MHz.
- For calculation of the timers' ResetValue according to the AXI Timer 2.0 LogiCORE IP Product Guide (PG079) using Matlab or Octave type:
- dec2hex(double(0xFFFFFFFF + 2) - timer_interval_in_sec * 100E6)
- while timer_interval_in_sec being the time the LED is off between the activation of the switch and the interrupt, that switches the LED on.