ARM32-BIT CPU — RTL Design (Verilog + SystemVerilog)

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Project Overview

This repository contains a complete ARM32-bit CPU designed using Verilog/SystemVerilog and verified using Vivado 2025.1 and EDAPlayground.
The CPU follows a simplified educational ARM architecture (from Harris & Harris: Digital Design and Computer Architecture — ARM Edition), implementing:

• 32-bit datapath
• Instruction Fetch → Decode → Execute flow
• ARM flags (N, Z, C, V)
• ALU operations — ADD, SUB, AND, OR
• Conditional execution
• Register file (R0–R15 with PC+8 behavior)
• IMEM (instruction memory)
• DMEM (data memory)
• Complete CPU integration with a testbench

All RTL modules are complete, functional, and verified.

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Module Details

ALU — Arithmetic Logic Unit

• Functions: ADD, SUB, AND, OR
• Inputs: SrcA[31:0], SrcB[31:0], ALUControl[1:0]
• Outputs: ALUResult[31:0], ALUFlags[3:0]
• Flags generated:
  • N (Negative)
  • Z (Zero)
  • C (Carry)
  • V (Overflow)
• Verified in EDAPlayground & Vivado

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Datapath

Includes:

• Program Counter (PC)
• PC increment logic (PC → PC+4 → PC+8)
• Register File (R0–R15)
• ALU
• Immediate Extender
• MUX structures
• Write-back path

Status: Verified and stable.

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Controller

Contains:

• Main decoder
• ALU decoder
• Conditional execution logic

Generates:

• RegWrite
• MemWrite
• ImmSrc
• ALUSrc
• FlagW
• MemtoReg
• PCSrc
• RegSrc

Status: Verified.

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Instruction Memory (IMEM)

• 64 × 32-bit

• Works correctly in EDAPlayground

• Vivado requires correct file placement

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Data Memory (DMEM)

• 64 × 32-bit RAM
• Write-enable controlled by MemWrite
• Verified.

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Top-Level CPU

Connects:

• Datapath
• Controller
• IMEM
• DMEM

Status: Fully functional CPU simulation achieved.

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CPU Architecture (Images to Upload on GitHub Later)

Datapath Diagram

RTL Architecture

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Compliance Checklist

Feature / Requirement	Status	Notes
32-bit ALU	Pass	ADD/SUB/AND/OR
ARM Flags N,Z,C,V	Pass	Matches ARM behavior
Register File	Pass	R15 = PC+8
Datapath	Pass	Verified
Instruction Memory	Pass	Loads from memfile.dat
Data Memory	Pass	Read/Write OK
EDAPlayground CPU Run	Pass	Fully successful
Vivado Compatibility	InProgress	memfile.dat must be placed manually
Testbench	Pass	Clock/Reset + CPU integration

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Directory Structure

ARM32_BIT_CPU/
│── adder.v
│── alu.v
│── condlogic.v
│── condcheck.v
│── controller.v
│── cpu.v
│── datapath.v
│── decoder.v
│── dmem.v
│── extend.v
│── flopr.v
│── flopenr.v
│── imem.v
│── memfile.dat
│── mux2.v
│── regfile.v
│── testbench.sv
│── top.v
└── README.md

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Simulation Instructions

Full CPU Simulation (EDAPlayground)

https://www.edaplayground.com/x/Hk54

Waveform Viewer (EPWave)

https://www.edaplayground.com/launchEpwave

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Vivado Simulation (Windows)

Important

Vivado does not automatically detect memfile.dat.
You must place it manually here:

PROJECT_NAME.srcs/sim_1/imports/memfile.dat

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Project Status

• All RTL modules implemented
• Full CPU simulation successful on EDAPlayground
• ALU and Datapath verified on Vivado
• Register file, memory, decoder, controller verified
• Suitable for portfolio, resume, and interviews
• Vivado requires proper memfile.dat placement

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Results

Edaplayground Simulation Result

Vivado ALU Waveform

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License

Released under the MIT License.

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Acknowledgments

• This project is derived from the educational ARM architecture presented in Digital Design and Computer Architecture — ARM Edition (Harris & Harris).
• Verified using Vivado, Icarus Verilog, and EDAPlayground.

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