Bugfix: Output Enable (oe_n) was inverted.

BugFix: Data going from A->B or B->A should be inverted.

Author: Ronny Hansen

Verilog/Shared/support/TTL_74648.v

@@ -7,7 +7,7 @@
  **                                                                          **
  ** DOC: https://www.ti.com/lit/ds/symlink/sn54as646.pdf                     **
  **                                                                          **
- ** Last reviewed: 7-DEC-2024                                                **
+ ** Last reviewed: 9-MAR-2025                                                **
  ** Ronny Hansen                                                             **
  ******************************************************************************/
 
@@ -55,8 +55,8 @@ module TTL_74648 (
   assign s_dir   = DIR;
   assign s_oe_n  = OE_n;
 
-  assign a_in_n  = ~A_IN;
-  assign b_in_n  = ~B_IN;
+  assign a_in_n  = A_IN;
+  assign b_in_n  = B_IN;
 
 
 
@@ -89,7 +89,7 @@ A_OUT:
 
   // s_sba = 0 => Real Time B to A
   // s_sba = 1 => Register  B to A
-  assign A_OUT_n = !s_oe_n ? 8'b0 : !s_dir ? ((!s_sba) ? ~b_in_n : ~regB) : 8'b0;
+  assign A_OUT_n = s_oe_n ? 8'b0 : !s_dir ? ((!s_sba) ? ~b_in_n : ~regB) : 8'b0;
 
 
   /*
@@ -105,6 +105,6 @@ B_OUT:
 
   // s_sab = 0 => Real Time A to B
   // s_sab = 1 => Register  A to B
-  assign B_OUT_n = !s_oe_n ? 8'b0 : s_dir ? ((!s_sab) ? ~a_in_n : ~regA) : 8'b0;
+  assign B_OUT_n = s_oe_n ? 8'b0 : s_dir ? ((!s_sab) ? ~a_in_n : ~regA) : 8'b0;
 
 endmodule