Refactor and cleanup to remove LINTER warnings

Author: Ronny Hansen

Verilog/CPU-BOARD-3202/circuit/BIF_BCTL_6.v

@@ -145,8 +145,6 @@ module BIF_BCTL_6 (
   wire       s_bperr50_n;
   wire       s_block25_n;
   wire       s_bdry75_n;
-  wire       s_act_n;
-  wire       s_dore_n;
   wire       s_mem_n;
   wire       s_cact25_n;
   wire       s_eiod_n;
@@ -270,9 +268,9 @@ module BIF_BCTL_6 (
       .MOFF_n   (s_moff_n),     // I7 - MOFF_n
 
       .SEM_n  (s_sem_n),   // Q0_n - SEM_n
-      .ACT_n  (s_act_n),   // Q1_n - ACT_n (n.c.)
-      .DOREF_n(s_dore_n),  // Q2_n - DOREF_n (n.c.)
-      .MEM_n  (s_mem_n),   // Q3_n - MEM_n (n.c.)
+      .ACT_n  (),          // Q1_n - ACT_n (n.c.)
+      .DOREF_n(),          // Q2_n - DOREF_n (n.c.)
+      .MEM_n  (s_mem_n),   // Q3_n - MEM_n
       .REF_n  (s_ref_n),   // Q4_n - REF_n
       .IOD_n  (s_iod_n),   // Q5_n - IOD_n
       .GNT_n  (s_gnt_n),   // Q6_n - GNT_n

Verilog/CPU-BOARD-3202/circuit/BIF_BCTL_BDRV_7.v

@@ -240,6 +240,10 @@ module BIF_BCTL_BDRV_7 (
   assign s_berror_n = s_tout ? s_Y2[2] : 1'b1;
   assign s_bdry_n   = s_tout ? s_Y2[3] : 1'b1;
 
+  // The following 2 lines is to make LINTER quiet as s_Y1[3] is unused/not connected
+  (* keep = "true", DONT_TOUCH = "true" *) wire unused_s_Y1_bit;
+  assign unused_s_Y1_bit = s_Y1[3];
+
 
   TTL_74241 CHIP_3A (
       .A1  (s_A1[3:0]),

Verilog/CPU-BOARD-3202/circuit/CPU_15.v

@@ -106,6 +106,8 @@ module CPU_15 (
     output IONI,         //! Interrupt System ON
     output RRF_n,        //! Output RRF signal from CPU to CYCLE
     output ECCR,         //! ECC Register Detected for IOX
+    output HIT,          //! Cache hit
+    output LEV0,         //! Level 0 active
 
     output LED1         //! Cache enabled ?
 );
@@ -346,6 +348,8 @@ module CPU_15 (
   assign IONI = s_ioni;
   assign RRF_n = s_rrf_n;
   assign ECCR = s_eccr;
+  assign HIT = s_hit;
+  assign LEV0 = s_lev0;
 
   assign LED1 = s_led1;
 

Verilog/CPU-BOARD-3202/circuit/CPU_MMU_CACHE_25.v

@@ -58,20 +58,17 @@ module CPU_MMU_CACHE_25 (
   wire [10:0] s_ca_10_0;
   wire [ 1:0] s_hit_1_0_n;
   wire        s_wca_n;
-  wire        s_led1;
   wire        s_brk_n;
   wire        s_wcinh_n;
   wire        s_used_n;
   wire        s_con;
   wire        s_con_n;
   wire        s_cclr_n;
-  wire        s_oubi;
   wire        s_hit;
   wire        s_dt_n;
   wire        s_lshadow;
   wire        s_cyd;
   wire        s_cwr;
-  wire        s_oubd;
   wire        s_uclk;
   wire        s_rt_n;
   wire        s_pd2;
@@ -203,6 +200,8 @@ module CPU_MMU_CACHE_25 (
       .IHIT_n()  //.Q3_n(s_ihit) // IHIT_n not connected
   );
 
+  assign s_21f_in[3:2] = 2'b00;
+
   Am9150 CHIP_21F (
       .clk            (sysclk),          // Clock input (BLOCK RAM MUST HAVE CLOCK)
       .address        (s_ca_10_0[9:0]),

Verilog/CPU-BOARD-3202/circuit/IO_37.v

@@ -18,6 +18,7 @@ module IO_37(
    input       BDRY50_n,
    input       BRK_n,
    input       CLK,
+   input       CONSOLE_n,
    input [4:0] CSCOMM_4_0,
    input [4:0] CSIDBS_4_0,
    input [1:0] CSMIS_1_0,
@@ -26,7 +27,6 @@ module IO_37(
    input       EAUTO_n,
    input       EORF_n,
    input       HIT,
-   input       I1P,
    input       ICONTIN_n,
    input       ILOAD_n,
    input [7:0] INR_7_0,
@@ -50,7 +50,6 @@ module IO_37(
    input       XTAL1,
    input       XTAL2,
    input       XTR,
-   input       CONSOLE_n,
 
    // Input and Output signals
    input  [7:0]  IDB_7_0_IN,
@@ -143,7 +142,6 @@ module IO_37(
    wire        s_swmcl_n;
    wire        s_rinr_n;
    wire        s_ceuart_n;
-   wire        s_i1p;
    wire        s_lcs_n;
    wire        s_refrq_n;
    wire        s_epans_n;
@@ -229,7 +227,6 @@ module IO_37(
    assign s_xtal2             = XTAL2;
    assign s_ioni              = IONI;
    assign s_swmcl_n           = SWMCL_n;
-   assign s_i1p               = I1P;
    assign s_lcs_n             = LCS_n;
    assign s_ref_n             = REF_n;
    assign s_uclk              = UCLK;
@@ -355,33 +352,33 @@ module IO_37(
       .sysclk(sysclk), // System clock in FPGA
       .sys_rst_n(sys_rst_n), // System reset in FPGA
 
-      .BAUD_RATE_SWITCH(BAUD_RATE_SWITCH),
+      // Input signals
       .CEUART_n(s_ceuart_n),
       .CLK(s_clk),
       .CONSOLE_n(s_uart_console_n),
-      .DA_n(s_da_n),
       .EAUTO_n(s_eauto_n),
       .EIOR_n(s_eior_n),
-      .I1P(s_i1p),
-      .IDB_7_0_IN(s_idb_7_0_in[7:0]),
-      .IDB_15_0_OUT(s_idb_15_0_uart_out[15:0]),
       .LCS_n(s_lcs_n),
       .LOCK_n(s_lock_n),
       .MIS_1_0(s_csmis_1_0[1:0]),
-
-      /* verilator lint_off PINMISSING */
-      /* verilator lint_off PINCONNECTEMPTY */
-      .O1P(), //O1P is unused
-      .O2P(), //O2P is unused
-      /* verilator lint_on PINCONNECTEMPTY */
-      /* verilator lint_on PINMISSING */
-
       .PPOSC(s_pposc),
       .RUART_n(s_ruart_n),
+      .XTR(s_xtr),
+
+      // RS232 RX/TX signals
       .RXD(s_rxd),
-      .TBMT_n(s_tbmt_n),
       .TXD(s_txd),
-      .XTR(s_xtr)
+
+      // Baud dare settings
+      .BAUD_RATE_SWITCH(BAUD_RATE_SWITCH),
+
+      // Input and output signals
+      .IDB_7_0_IN(s_idb_7_0_in[7:0]),
+      .IDB_15_0_OUT(s_idb_15_0_uart_out[15:0]),
+
+      // Output signals
+       .DA_n(s_da_n),
+      .TBMT_n(s_tbmt_n)
    );
 
 

Verilog/CPU-BOARD-3202/circuit/IO_PANCAL_40.v

@@ -45,7 +45,6 @@ module IO_PANCAL_40 (
    *******************************************************************************/
   wire [ 4:0] s_dp_5_1_n;
   wire [ 4:0] s_ground_bus;
-  wire [ 3:0] s_bus_4_bit;
   wire [ 4:0] s_stat_4_0;
   wire [ 1:0] s_pcr_1_0;
   wire [15:0] s_idb_15_0_out;
@@ -60,17 +59,12 @@ module IO_PANCAL_40 (
   wire        s_lev0;
   wire        s_emp_n;
   wire        s_panos;
-  wire        s_ck;
   wire        s_rmm_n;
   wire [15:0] s_idb_15_0_chip_out;
 
   wire        s_pres;
   wire        s_read;
 
-  /*******************************************************************************
-   ** The module functionality is described here                                 **
-   *******************************************************************************/
-
   /*******************************************************************************
    ** Here all input connections are defined                                     **
    *******************************************************************************/

Verilog/CPU-BOARD-3202/circuit/IO_UART_42.v

@@ -30,11 +30,6 @@ module IO_UART_42 (
     input  RXD,  //! RS232 Receive
     output TXD,  //! RS232 Transmit
 
-    // Current loop signals
-    input  I1P,  //! Current Loop Input 1
-    output O1P,  //! Current Loop Output 1
-    output O2P,  //! Current Loop Output 2
-
     // Baud rate settings
     input [3:0] BAUD_RATE_SWITCH,  //! Baud rate switch
 
@@ -66,7 +61,6 @@ module IO_UART_42 (
   wire        s_eauto_n;
   wire        s_eiorn_n;
   wire        s_gnd;
-  wire        s_i1p;
   wire        s_lcs_n;
   wire        s_lock_n;
   wire        s_pposc;
@@ -85,7 +79,6 @@ module IO_UART_42 (
    ** Here all input connections are defined                                     **
    *******************************************************************************/
   assign s_mis_1_0[1:0]          = MIS_1_0;
-  assign s_i1p                   = I1P;
   assign s_lock_n                = LOCK_n;
   assign s_ceuart_n              = CEUART_n;
   assign s_xtr                   = XTR;
@@ -108,8 +101,6 @@ module IO_UART_42 (
   assign s_io_idb_15_0_out[10:5] = 6'b0;
 
   assign TXD                     = s_txd;
-  assign O1P                     = s_txd;
-  assign O2P                     = s_txd;
 
   // Both DA and TBMT are pulled high
   // DA_n (or /RXRDY from UART) signal is only valid when the receiver is enabled
@@ -123,7 +114,7 @@ module IO_UART_42 (
    ** Here all in-lined components are defined                                   **
    *******************************************************************************/
   assign s_gnd                   = 1'b0;
-  assign s_rx                    = s_i1p | s_rxd;
+  assign s_rx                    = s_rxd;
 
 
   AM29C821 CHIP_33G (

Verilog/CPU-BOARD-3202/circuit/MEM_43.v

@@ -82,10 +82,8 @@ module MEM_43 (
   wire [17:0] s_ram_dd_17_0_in;  // INPUT TO MEM_DATA
   wire [17:0] s_ram_dd_17_0_out;  // OUTPUT FROM MEM_DATA
 
-  wire [19:0] s_lbd_19_0;
-
   wire [23:0] s_lbd_23_0_in;  // RAM DATA 16 bits and ADDRESS 24 bits
-  wire [23:0] s_lbd_23_0_out;  // RAM DATA 16 bits
+  wire [15:0] s_lbd_15_0_out;  // RAM DATA 16 bits
 
   wire        s_bcgnt50;
   wire        s_bcgnt50r_n;
@@ -156,7 +154,7 @@ module MEM_43 (
    *******************************************************************************/
   assign s_bus_bd[4:0]       = BD_23_19_n;
   assign s_bus_ppn[4:0]      = PPN_23_19;
-  assign s_lbd_23_0_in[23:0] = LBD_23_0_IN;
+  assign s_lbd_23_0_in[23:0] = LBD_23_0_IN[23:0];
   assign s_ibinput_n         = IBINPUT_n;
   assign s_pd3               = PD3;
   assign s_dbapr             = DBAPR;
@@ -199,7 +197,7 @@ module MEM_43 (
   assign MOFF_n              = s_moff_n;
   assign MOR25_n             = s_mor25_n;
   assign MWRITE_n            = s_mwrite_n;
-  assign LBD_23_0_OUT        = s_lbd_23_0_out;
+  assign LBD_23_0_OUT        = {8'b00000000, s_lbd_15_0_out};
 
 
   /*******************************************************************************
@@ -315,7 +313,7 @@ module MEM_43 (
       // Output signals
       .DD_17_0_OUT(s_data_dd_out[17:0]),
       .HIERR(s_hierr),
-      .LBD_15_0_OUT(s_lbd_23_0_out[15:0]),
+      .LBD_15_0_OUT(s_lbd_15_0_out[15:0]),
       .LED4(LED4),
       .LERR_n(s_lerr_n),
       .LOERR(s_loerr),

Verilog/CPU-BOARD-3202/circuit/MEM_DATA_46.v

@@ -24,7 +24,7 @@ module MEM_DATA_46 (
     input  [15:0] LBD_15_0_IN,
     output [15:0] LBD_15_0_OUT,
 
-    output [17:0] DD_17_0_IN,
+    input  [17:0] DD_17_0_IN,
     output [17:0] DD_17_0_OUT,
 
     // Output signals