cmov: add riscv32 optimised mask generation#1396
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tarcieri merged 1 commit intoRustCrypto:masterfrom Jan 18, 2026
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Nice, thanks!
It would be nice if there were some way to test it in CI, although AFAICT the only riscv32 Linux target is no more: rust-lang/rust#143440
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Same as #1396 but for `riscv64`. Add tests in CI with target `riscv64gc-unknown-linux-gnu`. Co-authored-by: Nics <NicsTr@users.noreply.github.com>
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Description of the changes brought by this commit
Currently, arm assembly is used to optimise for performance and have stronger guarantees that compiler optimisations will not insert branching during mask generation.
This commit introduces the same for the
riscv32architecture.I managed to run successfully some of
cmov's integration tests (the test inregressionand the 94 tests ofcore_impls) on a real target: a board with anesp32c6chip.Discussion on the state of constant time instructions of RISC-V machines
Additionally, it may be worth alerting the user of the state of constant time instruction in RISC-V: to my knowledge, a RISC-V machine is not guaranteed to have any constant time instructions in general. Only the machines declaring that they have the
Zktextension must guarantee that the given subset of instructions described in theZktspecification are constant time. In practice, a RISC-V machine may have constant time implementations for some or all "expected" instructions without declaring they support theZktextension.To be conservative, this crate should maybe be configured not to compile if the
zkttarget feature is not enabled. However, this is maybe too conservative since, AFAIK, there are not a lot of chip declaring that they support this extension.(Also, the
Zicondextension provides a new instruction similar tocselorcmov. If it is welcome here, I may work on a different PR adding a new backend for targets having thezicondfeature enabled)