🔍 VLSI Design Verification Engineer Projects

Welcome to my collection of VLSI Design Verification projects.
This GitHub repository showcases hands-on work in functional verification using SystemVerilog, UVM, and industry-standard EDA tools.

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📁 Repository Structure

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├── ALU_32bit_UVM/               # 32-bit ALU Design + UVM Verification
│   ├── rtl/
│   ├── tb/
│   └── README.md
│
├── FIFO_Verification/           # Synchronous FIFO Verification
│   ├── rtl/
│   ├── tb/
│   └── README.md
│
├── APB_Protocol_Checker/        # APB Protocol Checker (Assertion-based)
│   ├── sv/
│   └── README.md
│
├── Design_and_Verification_of_AXI_Slave_Protocol/          # AXI-Slave Protocol with FSM-based Testbench
│   ├── rtl/
│   ├── tb/
│   └── README.md

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🧪 Key Verification Skills Demonstrated

• ✅ UVM Environment Development (agent, monitor, driver, scoreboard)
• ✅ Functional Coverage and Constrained Random Testing
• ✅ Assertion-Based Verification (SVA)
• ✅ SystemVerilog Interface & Clocking Block Usage
• ✅ Directed & Randomized Testing
• ✅ Testbench Reusability & Modularity
• ✅ Scoreboarding and Functional Checks
• ✅ Simulation with ModelSim/QuestaSim

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🧰 Tools Used

• QuestaSim / ModelSim – Simulation
• SystemVerilog – Design & Verification Language
• UVM (Universal Verification Methodology) – Verification Framework
• Git/GitHub – Version Control & Collaboration

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🤝 Let's Connect

If you're a recruiter, engineer, or enthusiast, I'd love to connect!

• 🌐 LinkedIn
• ✉️ [email protected]

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📜 License

MIT License. Free to use with attribution. Contributions welcome!

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🚀 Built with curiosity and passion for VLSI Design Verification.