Chisel Wishbone NoC generator

This project is WIP and is not ready to be used.

The goal of this project is to make it easy and safe for Chisel SoC's to interconnect slaves and masters using the Wishbone protocol.

TODO

• Maintain a unit test suite for all supported features
• Point-to-point interconnnections
  • Trivially supported with a Bundle
• Shared-bus interconnnections
  • Discontinuous and individually-sized slave memory maps
    • Benchmark partial address decoding against current implementation
  • Verify slave protocol compliance at simulation time
    • Assert that ¬STB_I → ¬ACK_O
  • Verify master protocol behaviour at simulation time
    • Assert if a master hogs the bus for x cycles
  • User-friendly support for normal segmented memory maps
  • Multiple arbitration strategies
• Crossbar interconnnections
• Make the generated code more readable