Modified from SiEPICfab_ZEP04_Shuksan_20250215 README.md

Download the entire floorplan_example folder before continuing

Submission Process Slightly modified

We are using an automated merging script to combine the layouts.

Step 1: In this step, you allocate yourself space in the shared design space.

Step 2: In this step, you create your personal design layout function using "Bragg Reflector.ipynb" as an example. Commit your changes as your design changes.

Step 3: In this step, you merge your design layout file to the merged layout file to be submitted.

Detailed instructions:

Step 1:

• Pull from GitHub the repo
• Open 'gds_floorplan'.
• Open the floorplan layout file inside the folder.
• Create a box using the 'FloorPlan' layer in which your design will fit in.
• Turn the box into a cell with your name (Ctrl+Shift+M), Edit → Selection → Make Cell
• Save the layout
• IMPORTANT Commit back to GitHub.

Step 2:

• Open the notebook example: "Bragg Reflector.ipynb"
• Change the PDK location
• This copys the floorplan from the mainchip floorplan .oas file in gds_floorplan
• Adjust accordingly, ie Pcells is def
• Comments in the example should walk you through whats necessary
• IMPORTANT Commit back to GitHub.

Step 3:

• Run the Python script 'merge_layouts.py'
• Check if your design has been merged in the 'gds_merge' layout file
• IMPORTANT Commit back to GitHub.