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How to use external JTAG (CMSIS-DAP) with Vexii MicroSoc? (Beginner)

Status: Open.

#105 In SpinalHDL/VexiiRiscv;

· princesuman2004 opened on Jan 9, 2026

Examples for simulate SoC with spi flash?

Status: Open.

#102 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Dec 22, 2025

There is an inconsistency in mie.LCOFIE

Status: Open.

#96 In SpinalHDL/VexiiRiscv;

· fly-1011 opened on Nov 16, 2025

Trying to connect a LsuL1Cmd port from external units (like CFU) to CPU

Status: Open.

#80 In SpinalHDL/VexiiRiscv;

· Jzjerry opened on Sep 3, 2025

[Feature request] Zmmul extension, no division

Status: Open.

#73 In SpinalHDL/VexiiRiscv;

· jrmoserbaltimore opened on Aug 22, 2025

MicroSoC generation failing with CFU plugin

Status: Open.

#71 In SpinalHDL/VexiiRiscv;

· Rishu31 opened on Aug 20, 2025

Disable LSU Cache on LiteX SoC

Status: Open.

#68 In SpinalHDL/VexiiRiscv;

· mkuhn99 opened on Aug 1, 2025

How to tunnel VexiiRiscv Debug port using BSCANE2?

Status: Open.

#58 In SpinalHDL/VexiiRiscv;

· Matze584 opened on May 27, 2025

[Feature Request] Vector extensions

Status: Open.

#57 In SpinalHDL/VexiiRiscv;

· jrmoserbaltimore opened on May 24, 2025

"Hello world" tutorial fails to compile

Status: Open.

#56 In SpinalHDL/VexiiRiscv;

· NikkiOfTheValley opened on May 23, 2025

Support for vectored interrupt mode?

Status: Open.

#53 In SpinalHDL/VexiiRiscv;

· Matze584 opened on Apr 20, 2025

How to extract RS1/RS2 value for debugging?

Status: Open.

#46 In SpinalHDL/VexiiRiscv;

· esyvjlomh opened on Mar 19, 2025