In Autumn 2023, I participated in TinyTapeout 04 and submitted a Verilog design to tapeout a real chip.
The original code contained several bugs that would affect the correct functionality of the design. This repository contains the corrected version.
- LFSR reset initialized to all-zeros (lock-up state) → fixed to non-zero seed
- Added Clock Divider
A Pseudo Random Number Generator (PRNG) based on two LFSRs and a 16-to-8 multiplexer, designed for TinyTapeout 04.
https://github.com/Spiros7bit/tt04-submission-test
- Quartus II Web Edition 13.01
- ModelSim ALTERA STARTER EDITION 10.1d
