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ACC_REGISTER.v
ACC_REGISTER.v
 
 
ALU.v
ALU.v
 
 
ALU_ADDER.v
ALU_ADDER.v
 
 
ALU_AND.v
ALU_AND.v
 
 
ALU_BUFFER.v
ALU_BUFFER.v
 
 
ALU_NOT.v
ALU_NOT.v
 
 
ALU_OR.v
ALU_OR.v
 
 
ALU_SHL.v
ALU_SHL.v
 
 
ALU_SHR.v
ALU_SHR.v
 
 
ALU_XOR.v
ALU_XOR.v
 
 
ALU_tb_SHL.v
ALU_tb_SHL.v
 
 
AND.v
AND.v
 
 
AND3inp.v
AND3inp.v
 
 
AND4inp.v
AND4inp.v
 
 
AND8inp.v
AND8inp.v
 
 
AND8inp_END.v
AND8inp_END.v
 
 
CONTROL_UNIT.v
CONTROL_UNIT.v
 
 
CPU.v
CPU.v
 
 
DISP_REGISTER.v
DISP_REGISTER.v
 
 
END_STOP_INSTRUCTION.v
END_STOP_INSTRUCTION.v
 
 
FLAGS_REGISTER.v
FLAGS_REGISTER.v
 
 
FLAG_CHECKER.v
FLAG_CHECKER.v
 
 
FREQUENCY_DIVIDER.v
FREQUENCY_DIVIDER.v
 
 
Fibonacci_series.v
Fibonacci_series.v
 
 
GPR_REGISTER.v
GPR_REGISTER.v
 
 
IAR_REGISTER.v
IAR_REGISTER.v
 
 
IR_REGISTER.v
IR_REGISTER.v
 
 
MICRO_INSTRUCTION.v
MICRO_INSTRUCTION.v
 
 
NAND.v
NAND.v
 
 
NOR.v
NOR.v
 
 
NOT.v
NOT.v
 
 
OPCODE.v
OPCODE.v
 
 
OR.v
OR.v
 
 
OR256inp.v
OR256inp.v
 
 
OR3inp.v
OR3inp.v
 
 
OR4inp.v
OR4inp.v
 
 
OR5inp.v
OR5inp.v
 
 
OR6inp.v
OR6inp.v
 
 
RAM_module.v
RAM_module.v
 
 
RAM_vs_CPU.v
RAM_vs_CPU.v
 
 
README.md
README.md
 
 
RECEIVE_CONTROL.v
RECEIVE_CONTROL.v
 
 
REGISTERS.v
REGISTERS.v
 
 
SEND_CONTROL.v
SEND_CONTROL.v
 
 
SEQUENCER.v
SEQUENCER.v
 
 
TEMP_register.v
TEMP_register.v
 
 
XNOR.v
XNOR.v
 
 
XOR.v
XOR.v
 
 
ZERO_REGISTER.v
ZERO_REGISTER.v
 
 
adder.v
adder.v
 
 
decoder2x4.v
decoder2x4.v
 
 
decoder3x8.v
decoder3x8.v
 
 
decoder4x16.v
decoder4x16.v
 
 
delay_NOT.v
delay_NOT.v
 
 
delay_Oclk_Iclk.v
delay_Oclk_Iclk.v
 
 
dummy_clk.v
dummy_clk.v
 
 
inp8mux2x1.v
inp8mux2x1.v
 
 
mem_DFF.v
mem_DFF.v
 
 
mem_buf.v
mem_buf.v
 
 
mem_register.v
mem_register.v
 
 
mux256x1_0.v
mux256x1_0.v
 
 
mux2x1.v
mux2x1.v
 
 
reg_DFF.v
reg_DFF.v
 
 
register_ip_controlled.v
register_ip_controlled.v
 
 

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set "Fibonacci_series.v" as top module and run the simulation. Note: -adjust 'divisor' parameter in FREQUENCY_DIVIDER.v accordingly. -if you want to run this on FPGA then lookout for clock frequency of that FPGA.

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