[pull] master from YosysHQ:master #372
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Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
…r better interoperability with other synthesis tools and RTL languages
* Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks. And the style edits - they get automatically when I make sure to run clang-format10. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix the port check for connectivity. What happens is that it's not enough to check for a network, we also need to make sure that the network is functional: has src and sinks Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
* apicula: add support for magic sip pins * fix nullptr check * DDR fix by xiwang * WIP support for setting the iostd * add iostd
Signed-off-by: gatecat <[email protected]>
Signed-off-by: gatecat <[email protected]>
* Gowin. FFs placement. * Allow clusters to be created from FFs and LUTs; * Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs; * In case of constant networks, such pass-through LUTs are disconnected from networks altogether; * Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading. Signed-off-by: YRabbit <[email protected]> * Gowin. Fix aux name creation Signed-off-by: YRabbit <[email protected]> * Gowin. Use I3 for pass-trough LUTs Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>
* Extend Himbaechel API with gfx drawing methods * Add bel drawing in example uarch * changed API and added tile wire id in db * extend API so we can distinguish CLK wires * added bit more wires * less horrid way of handling gfx ids * loop wire range * removed not needed brackets * bump database version to 5 * Removed not used GfxFlags
* Add expandBoundingBox method to API * Update API documentation
Add sampling part to IO blocks (input only). This edge detector will allow to dynamically adjust DDR decoding window in the future. Signed-off-by: YRabbit <[email protected]>
* Gowin. Add IODELAY. Input/Output delay (IODELAY) is programmable delay uint in IO block. This delay line is enabled before/after the IO pad and allows the signal to be delayed statically or dynamically during 0-127 stages each lasting from 18 to 30 picoseconds depending on the chip family. Signed-off-by: YRabbit <[email protected]> * Gowin. Replacing assertions with log_error. Signed-off-by: YRabbit <[email protected]> --------- Signed-off-by: YRabbit <[email protected]>
* ng-ultra: new architecture * Implementation as in D2 deliverable * Support for nxdesignsuite-24.0.0.0-20240429T102300 * Save memory by directly outputing json * Add support for bidirectional IOs * cleanup * Create BFRs properly * Add IOM insertion * Cleanup * Block certain pips depending of DDFR mode * Add LUT bypass to improve routability * Add bypass for CSC mode of GCK * Fix IOM case * Initial memory support * Better RF/XRF handling * fix * RF placement and legalization * Disconnect non available ports for NX_RAM * cleanup * Add RFB/RAM context support for latest release * Remove ports that must not be used * Proper port used only on RFB * Add structure for clock sinks * Use cell type where applicable * Add clock sinks for other cell types * Validation check fixes * Commented too restrictive placement * Added more crossbar wire type * Hande IO termination input * Fail early due to NX tools limitation for now * Validations and fixes for RAM I/Os * Fix for latest version of tools * Use ctx->idf where applicable * warn if RAM ports are not actually used * Fix IOM packing * Fix CY packing * Change how constants are handled on CY * Post placement optimization for CY * Address comments for PR * pack and export GCK, WFG and PLL * Cover more global routing cases * Constraing to location if provided * Place at LOC * Pack and export DSP * wip * wip * notes * wip * wip * Validate DSPs * DSP cascading * Check mandatory parameters for DSP * existing gck * wip * export all the rest for bitstream * CDC packing * add more sinks * place FIFO * map rest of FIFO ports * enable pll by default * cleanup * Initial XLUT support * Fix statistics * Properly duplicate GCKs * RRSTO and WRSTO are not used on XFIFO * Fix for latest version of JSON format * Implement GCK limitations * cleanup * cleanup * Add more signals and use lowskew name * cleanup code a bit * Fix wfb * detect cascaded GCKs * Handle DFR * Route dfr clock properly * Cleanup * Cleanup bitstream code * Review issues addressed * Move helper routines * Expose private members for unit tests * cleanup * remove scale factor * make all location helper arrays static * Addressed review comments * Support post-routing CSC and SCC * Support NX_BFF * Place CSS and SCC only on allowed locations * Support latest Impulse * ng_ultra: Expand bounding box further for left-edge IO Signed-off-by: gatecat <[email protected]> * Export all IO parameters in bitstream * Handle new CSV order or parameters and additional validation * Add some more undocumented values for CSV * Support for old and new CSV formats * Initial DDFR support * Display warning message once per file * Address review issues * Fix crash on memory access * Make boundbox fit NG-Ultra internal design * Update attributes after dff rewrite * Implement basic NG-Ultra LUT-DFF unit tests * Always use first seen xbar input Signed-off-by: gatecat <[email protected]> * Simplified crossbar pip detection * Change order to prevent issues with some unconnected constants * Pack LUT and multiple DFF in stripe * Place DFF chains * Improve large DFF chains * Rename to pack_dff_chains * Better use XLUTs when possible * pack output DFF together with XLUT * option to disable XLUT optimiziations * Make more optimizations optional * fix to use pre-increment * GCK for lowskew signals * Bugfix for nets that are not part of lowskew network * Fix bitstream export for PLL cell * Remove separate route lowskew * Allow WFG mode 2 * Merge inverter into GCK * Add CSC per TILE when needed * Improve reusage of existing cell for CSC * Take preferred CSC * Cleanup * When in place CSC size not important * Cleanup * Reset and Load restriction * make csc optimisation optional * Proper count for IO resources * Detect when there is no next cell for DSP chain * Do not incorporate loops in XLUT * Check if output exists * Update copyright for delivery * Make building NG-Ultra chip database optional, follow filename convention * Ported drawing code to new API * Update expandBoundingBox for NG-Ultra * Copyright and license update * Add README information * cleanup and constids * Using ctx->idf where applicable * remove if_using_basecluster * refactor extra data usage * refactor to use create_cell_ptr only * optimized getCSC * optimize critical path a bit * clangformat * disable clangformat where applicable --------- Signed-off-by: gatecat <[email protected]> Co-authored-by: Lofty <[email protected]> Co-authored-by: gatecat <[email protected]>
* Add GroupId related calls to Himbaechel API * Example uarch using new API features * Update drawGroup to propagate only GroupId
* Adds attributes to the hierarchical cells * python: add binding for hierarchical cells attributes * frontend/base: import hierarchical cells attributes
Adds additional restrictions on the first PIP after the clock source - only connections to SPINEs are allowed. This allowed to correct the behaviour of DQCEs since the latter can only disable/enable SPINEs. Signed-off-by: YRabbit <[email protected]>
…parated by a comma (#1571)
* rust: formatting cleanup * rust: explicitly mark as ISC license * rust: use std::ffi C types instead of libc dependency
In the GW5A series, the primitive SemiDual Port BSRAM cannot function when the width of any of the ports is 32/36 bits - it is necessary to divide one block into two identical ones, each of which will be responsible for 16 bits. Here, we perform such a division and, in addition, ensure that the new cells resulting from the division undergo the same packing procedure as the original ones. Naturally, with some reservations (the AUX attribute is responsible for this) - in the case of SP, when service elements are added, it makes sense to do this immediately for 32-bit SP and only then divide. Also, SDPs are currently being corrected for cases where both ports are ‘problematic’, but it may happen that one port is 32 and the other is, say, 1/2/4/8/16. This has been left for the future. Signed-off-by: YRabbit <[email protected]>
* Use QtPropertyBrowser for Qt5/6 * Fix cmake for python-console for consistency * Make GUI compile for both Qt5 and Qt6 * Fix crash on init with Wayland on Qt6 * Cleanup * disable deprecation warnings for now * Relaxed cmake check for initial Qt6 test
* gatemate: support multiple clock distribution strategies * error out on non supported cases * Implement full use strategy * Address review comments
* gatemate: document clock distribution strategies * gatemate: rename option to strategy
Co-authored-by: OpenProgger <[email protected]>
* remove copy of googletest from 3rdparty * Add googletest as submodule * Use googletest v1.17.0 * Update main CMakeLists.txt
Paired with YosysHQ/yosys@6535995 now that we may receive unattached OBUFs, we ignore them. Signed-off-by: YRabbit <[email protected]>
* gatemate: Use GATEMATE_DIE attribute to select placement die * add DIE parameter in CCF * add penalty delay when crossing between dies * Add predictDelay
* himbaechel: add uarch specific options parsing * fix tests * add reference to additional help * review comments addressed * cleanup and unify other uarch * Adressed PR comments
Signed-off-by: gatecat <[email protected]>
Since ctx->getArchArgs() no longer returns architecture-specific arguments, we read the args field directly. Signed-off-by: YRabbit <[email protected]>
* Cleanup Context API * Remove exit to prvent crash
* gatemate: handle default parameters for IO This is probably a VHDL specific issue. In VHDL, there is no black-box. Primitive instantiations are done using VHDL component instantiations and the component must have been declared with all its ports and parameters (generic). Currently the components are translated from cells_sim.v and cells_bb.v If a user doesn't override a parameter, the default value is used instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER or SLEW parameters of CC_IOBUF. I think this is a main difference with verilog, where unspecified parameters do not appear. With this change, the UNPLACED value of PIN_NAME and UNDEFINED value of DRIVE are simply ignored. * gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW
ADC support for GW5A-25 chips has been added. The inputs of this primitive are fixed and do not require routing, although they can be switched dynamically. The .CST file also specifies the pins used as signal sources for the bus0 and bus1 ADC buses. Signed-off-by: YRabbit <[email protected]>
The TLVDS_IBUF_ADC IO primitives have been implemented, which provide a signal for ADC bus 2. These differential IO primitives also have an additional input that allows them to be disabled, thereby providing dynamic switching of the signal source for the ADC. Signed-off-by: YRabbit <[email protected]>
* small cleanup * gatemate: pack output flops for multipliers * remove possibly-inaccurate comments
This connection is implicit as it is hardwired in the hardware. This commit makes the connection explicit and thus appearing in the generated netlist allowing post-rout simulation.
Adds LUT permutation support
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