Fix response error when read-only and write-only registers overlap

[sbaillou]

Description of change

Fixes #178 by flipping the polarity of the invalid_rw check. Instead of checking if an access is invalid, I now check if a valid access is performed.
If an access is performed to an existing address, but no valid R/W is performed, I then assert the error flag.

Note 1: I updated the error test by removing unnecessary external register tests, but replacing them with tests for external blocks (where we never asserts errors for bad RW access).

Note 2: I had to revert the change in the test_parity test #182 for Xilinx, as it seems to behave differently with force/release.

Checklist

• I have reviewed this project's contribution guidelines
• This change has been tested and does not break any of the existing unit tests. (if unable to run the tests, let us know)
• If this change adds new features, I have added new unit tests that cover them.