Add Wishbone Bus CPU Interface Exporter#196
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Nice! Just missing one thing - add the wishbone page to the top-level toctree: |
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Thanks @amykyta3, I added it :) |
amykyta3
approved these changes
Mar 17, 2026
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Changes
This PR adds a Wishbone Bus CPU Interface Exporter (mod and flat).
The interface implements SINGLE READ and SINGLE WRITE operations and has a stall port for pipelined operations.
This PR is an adaptation of a previous PR to the vhdl fork. I moved this PR upstream as requested by @darsor .
I have added unit tests for both configurations.