Fix missed elaboration of signal's 'external' property. #245

SystemRDL · Jan 7, 2025 · 186236c · 186236c
1 parent 056f33f
commit 186236c
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Showing 4 changed files with 23 additions and 11 deletions.
diff --git a/src/systemrdl/__about__.py b/src/systemrdl/__about__.py
@@ -1 +1 @@
-__version__ = "1.29.0"
+__version__ = "1.29.1"
diff --git a/src/systemrdl/core/elaborate.py b/src/systemrdl/core/elaborate.py
@@ -564,6 +564,13 @@ def enter_Field(self, node: FieldNode) -> None:
         assert node.parent is not None
         node.inst.external = node.parent.inst.external
 
+    def enter_Signal(self, node: SignalNode) -> None:
+        if isinstance(node.parent, RootNode):
+            # In root scope. External is meaningless, so assign it to False
+            node.inst.external = False
+        else:
+            assert node.parent is not None
+            node.inst.external = node.parent.inst.external
 
     def enter_Regfile(self, node: RegfileNode) -> None:
         if self.coerce_external_to is not None:

diff --git a/test/rdl_src/internal_external.rdl b/test/rdl_src/internal_external.rdl
@@ -1,3 +1,4 @@
+signal {} test_signal;
 
 addrmap extern_test {
     reg rega_t {field {} x;} external reg1, reg2;
@@ -31,4 +32,4 @@ addrmap extern_test {
     external rfile2_t rf2a;
     internal rfile2_t rf2b;
     rfile2_t rf2c;
-};
+};
diff --git a/test/test_external.py b/test/test_external.py
@@ -24,14 +24,18 @@ def test_basic(self):
             "reg12" : False,
         }
 
-        for name,external in extern_map.items():
+        for name, external in extern_map.items():
             with self.subTest(name):
                 reg = root.find_by_path("extern_test.%s" % name)
-                self.assertEqual(reg.external, external)
+                self.assertIs(reg.external, external)
 
         with self.subTest("addrmap"):
             addrmap = root.find_by_path("extern_test")
-            self.assertEqual(addrmap.external, True)
+            self.assertIs(addrmap.external, True)
+
+        with self.subTest("signal"):
+            signal = root.find_by_path("test_signal")
+            self.assertIs(signal.external, False)
 
 
     def test_regfile(self):
@@ -55,10 +59,10 @@ def test_regfile(self):
             "rf1c.regc"  : False,
         }
 
-        for name,external in extern_map.items():
+        for name, external in extern_map.items():
             with self.subTest(name):
                 reg = root.find_by_path("extern_test.%s" % name)
-                self.assertEqual(reg.inst.external, external)
+                self.assertIs(reg.inst.external, external)
 
     def test_nested_regfile(self):
         root = self.compile(
@@ -81,15 +85,15 @@ def test_nested_regfile(self):
             "rf1c.regc"  : False,
         }
 
-        for name,external in rf1_extern_map.items():
+        for name, external in rf1_extern_map.items():
             with self.subTest("rf2a.%s" % name):
                 reg = root.find_by_path("extern_test.rf2a.%s" % name)
-                self.assertEqual(reg.inst.external, True)
+                self.assertIs(reg.inst.external, True)
 
             with self.subTest("rf2b.%s" % name):
                 reg = root.find_by_path("extern_test.rf2b.%s" % name)
-                self.assertEqual(reg.inst.external, False)
+                self.assertIs(reg.inst.external, False)
 
             with self.subTest("rf2c.%s" % name):
                 reg = root.find_by_path("extern_test.rf2c.%s" % name)
-                self.assertEqual(reg.inst.external, external)
+                self.assertIs(reg.inst.external, external)