feat(model): add SenseNova U1.5 pixel-flow support

[CjhHa1]

Summary

Add trainside FlowGRPO support for SenseNova-U1.5 pixel flow so the released 8B MoT checkpoint can roll out, replay, and train inside UniRL without a VAE.

• Vendor the pinned OpenSenseNova NEO-Unify definitions (a62fd54) and wrap them in a checkpoint-compatible bundle / FSDP-callable facade.
• Implement packed RGB pixel-flow sampling that matches official t2i_generate: resolution-dependent noise scale, CFG (none / global / channel / cfg_zero_star), bf16 deterministic Euler, and unit-noise FlowSDE transitions for stochastic log-probs.
• Carry per-sample prefix KV caches as typed conditions, including device movement with the batch.
• Add the 8B trainside Hydra recipe (diffusion/sensenova_u1_5/sensenova_u1_5_trainside), freeze the understanding path, and train fm_modules.* plus every *_mot_gen branch under FSDP2.

vLLM-Omni rollout is the stacked follow-up in #393.

Related Issue

N/A

Test Plan

• SKIP=no-commit-to-branch pre-commit run --files $(git diff --name-only --diff-filter=ACMR origin/main --) --show-diff-on-failure — passed after merging current main.

• python3.12 -m compileall -q unirl

• Compose the trainside recipe:

  python -m unirl.train_diffusion \
    --config-name=diffusion/sensenova_u1_5/sensenova_u1_5_trainside \
    --cfg job --resolve

• Load SenseNova-U1.5-8B-MoT-Preview on H20 and run packed pixel-flow inference

• Full-checkpoint SDE replay/backward with finite gradients

• 32-GPU / 4-node FSDP optimizer step and checkpoint-resume smoke

• Official 512×512 CFG=4 50-step output matches tensor-for-tensor

Verification harnesses are intentionally not committed per repository policy. The larger packing, schedule-conversion, CFG, and cache-movement harness removed in a7352cc remains in the stacked vLLM-Omni follow-up #393.

Compatibility / Risk

• The SenseNova package and recipe are additive; shared algorithm and ReplayResult interfaces remain unchanged.
• Vendored neo_unify/ is excluded from ruff and pre-commit, same pattern as Bagel.
• The documented recipe pins attention_backend: sdpa. The vendor flash path is Flash-Attention 2; UniRL's engine extras ship Flash-Attention 4. attention_backend="flash" is rejected. auto still follows the vendor dispatcher (FA2 if flash_attn imports).
• Interleaved MoT layers mix frozen understanding and trainable generation params, so FSDP2 masters stay fp32 and compute is bf16 mixed precision. The recipe also sets root_wrap: true so fm_modules is covered.
• Trainside rollout is per-sample (forward_batch_size: 1) because prefix caches and packed pixel trajectories are not batched.
• Scope is T2I trainside FlowGRPO only. Image editing, LoRA, and engine rollout are out of this PR.

Reviewer Notes

• Start with unirl/models/sensenova_u1/diffusion.py: UniRL σ-time ↔ vendor data-time (t = 1-σ), unit-noise SDE vs bf16 Euler, and CFG reduction.
• Vendor pin and update steps are in unirl/models/sensenova_u1/vendor/VENDOR_COMMIT.txt. UniRL-owned seams outside the pristine subtree are the bundle/pipeline/stage, plus transformers_compat.py and the attention-backend guard.
• Suggested reading order: recipe YAML → bundle.py trainability/FSDP facade → diffusion.py → conditions.py cache movement → pixels.py pack/unpack.
• Duplicate-work check: the only overlapping open PR is feat(sensenova): add vLLM-Omni rollout #393, which stacks on this branch for vLLM-Omni rollout.
• AI assistance: Codex reviewed the full diff and helped remove unused cross-model algorithm plumbing; the commands above were rerun after merging current main.

Checklist

• I reviewed the changed code and removed unrelated/generated artifacts.
• I updated tests, docs, and configs where needed, or explained why not.

[leviking98z-rgb]

LGTM