Aspycot is a platform allowing rapid prototyping and early-validation of hardware monitoring IPs in standalone mode. It automates the compiling of applications and uses an instruction set simulator (ISS) to get execution traces. The traces are used as input stimuli for the hardware IP, whose behavior is checked in respect to a certain execution (or threat) model.
Aspycot is based on components from the open source ecosystem:
- RISC-V gcc toolchain
- Spike RISC-V ISS
- cocotb
You need the following tools:
- A RISC-V compiler
- Spike ISS
- cocotb (currently aspycot used cocotb 1.9.2)
- a HDL simulator supported by cocotb (verilator for Verilog/SystemVerilog, GHDL for VHDL ...)
- pytest
And then you can use the platform with the example from the associated article:
git clone aspycot
make ip=jop_alarm bmarks=hello_world,jop10Documentation is available at docs on how to extend the platform with new applications, threat models or IPs.
If you are interested in contributing to Aspycot, start by reading the Contributing guide.
The License is GPLv3. See LICENSE for more information.
Aspycot was presented in RAPIDO'25 workshop and the article will soon be available on ACM.