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Fix mispelled signals and missing pins#2

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cfuguet wants to merge 8 commits into
ThalesSiliconSecurity:pr/master_candidate_initial_oldfrom
cfuguet:pr/master_candidate_initial
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Fix mispelled signals and missing pins#2
cfuguet wants to merge 8 commits into
ThalesSiliconSecurity:pr/master_candidate_initial_oldfrom
cfuguet:pr/master_candidate_initial

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@cfuguet

@cfuguet cfuguet commented Jun 14, 2025

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When compiling with Verilator, it alerts about different errors. Some of these are fixed in this PR.

@cfuguet cfuguet requested a review from JeanRochCoulon as a code owner June 14, 2025 15:37
@cfuguet

cfuguet commented Jun 14, 2025

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@yanicasa

@yanicasa

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Thanks for your fixes, I think I need to check also FPGA Top.

@yanicasa yanicasa changed the base branch from pr/master_candidate_initial to pr/master_candidate_initial_old June 17, 2025 07:24
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