feat: update project tt_um_urish_simon from urish/tt10-simon-game

Commit: abcf605dc7b38c69764d32ab47bd92f6fa085b71
Workflow: https://github.com/urish/tt10-simon-game/actions/runs/12483024424

Author: TinyTapeoutBot

projects/tt_um_urish_simon/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt10 d89635e1",
   "repo": "https://github.com/urish/tt10-simon-game",
-  "commit": "2a1b9db329e70c1a1238c3e2dc559d441da85549",
-  "workflow_url": "https://github.com/urish/tt10-simon-game/actions/runs/12467975214",
+  "commit": "abcf605dc7b38c69764d32ab47bd92f6fa085b71",
+  "workflow_url": "https://github.com/urish/tt10-simon-game/actions/runs/12483024424",
   "sort_id": 1734941984438,
   "openlane_version": "OpenLane2 2.2.9",
   "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

projects/tt_um_urish_simon/stats/metrics.csv

@@ -10,14 +10,14 @@ synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,13
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00008426119893556461
-power__switching__total,0.00008628072100691497
-power__leakage__total,1.3447362334773061E-8
-power__total,0.0001705553731881082
+power__internal__total,0.00011479412205517292
+power__switching__total,0.00009810394112719223
+power__leakage__total,1.3440351054327948E-8
+power__total,0.00021291151642799377
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.2684622600211231
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.26723574109998016
 timing__hold__ws__corner:nom_tt_025C_1v80,0.3139363857732021
-timing__setup__ws__corner:nom_tt_025C_1v80,11.205900524680313
+timing__setup__ws__corner:nom_tt_025C_1v80,2.4032061465501093
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -26,32 +26,32 @@ timing__hold_vio__count__corner:nom_tt_025C_1v80,0
 timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.313936
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
+timing__setup_r2r__ws__corner:nom_tt_025C_1v80,2.403206
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
 design__max_slew_violation__count__corner:nom_ss_100C_1v60,12
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,13
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.27477418340596227
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.27321171098806635
-timing__hold__ws__corner:nom_ss_100C_1v60,0.8465604012967849
-timing__setup__ws__corner:nom_ss_100C_1v60,9.157651784977771
+timing__hold__ws__corner:nom_ss_100C_1v60,0.7371454766348562
+timing__setup__ws__corner:nom_ss_100C_1v60,1.8703839006998735
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
 timing__setup__wns__corner:nom_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.846560
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.737145
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_vio__count__corner:nom_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,12.270158
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,1.870384
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,13
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.26557562456430683
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.26366548579641685
 timing__hold__ws__corner:nom_ff_n40C_1v95,0.1175358732498305
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.38190907073331
+timing__setup__ws__corner:nom_ff_n40C_1v95,2.573211272449959
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -60,15 +60,15 @@ timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
 timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.117536
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
+timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,2.573211
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count,12
 design__max_fanout_violation__count,13
 design__max_cap_violation__count,0
 clock__skew__worst_hold,-0.2631546444127636
 clock__skew__worst_setup,0.2620554125649939
 timing__hold__ws,0.11458473383345921
-timing__setup__ws,9.111396339750016
+timing__setup__ws,1.8703839006998735
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -77,7 +77,7 @@ timing__hold_vio__count,0
 timing__hold_r2r__ws,0.114585
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,12.182004
+timing__setup_r2r__ws,1.870384
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -149,7 +149,7 @@ design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.2658409678746967
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.26515451695915676
 timing__hold__ws__corner:min_tt_025C_1v80,0.3112134527059966
-timing__setup__ws__corner:min_tt_025C_1v80,11.218253310490864
+timing__setup__ws__corner:min_tt_025C_1v80,2.4032061465501093
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -158,7 +158,7 @@ timing__hold_vio__count__corner:min_tt_025C_1v80,0
 timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.311213
 timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
+timing__setup_r2r__ws__corner:min_tt_025C_1v80,2.403206
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__unannotated_net__count__corner:min_tt_025C_1v80,74
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
@@ -167,17 +167,17 @@ design__max_fanout_violation__count__corner:min_ss_100C_1v60,13
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.27183875364583376
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.2702556310790957
-timing__hold__ws__corner:min_ss_100C_1v60,0.8407179634867621
-timing__setup__ws__corner:min_ss_100C_1v60,9.20731339454141
+timing__hold__ws__corner:min_ss_100C_1v60,0.7371454766348562
+timing__setup__ws__corner:min_ss_100C_1v60,1.8703839006998735
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
 timing__setup__wns__corner:min_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:min_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.840718
+timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.737145
 timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:min_ss_100C_1v60,12.370070
+timing__setup_r2r__ws__corner:min_ss_100C_1v60,1.870384
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__unannotated_net__count__corner:min_ss_100C_1v60,74
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
@@ -187,7 +187,7 @@ design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.2631546444127636
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.2620554125649939
 timing__hold__ws__corner:min_ff_n40C_1v95,0.11458473383345921
-timing__setup__ws__corner:min_ff_n40C_1v95,11.389878695918675
+timing__setup__ws__corner:min_ff_n40C_1v95,2.573211272449959
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -196,7 +196,7 @@ timing__hold_vio__count__corner:min_ff_n40C_1v95,0
 timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.114585
 timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
+timing__setup_r2r__ws__corner:min_ff_n40C_1v95,2.573211
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:min_ff_n40C_1v95,74
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
@@ -206,7 +206,7 @@ design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.27294015042856273
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.2698539523774261
 timing__hold__ws__corner:max_tt_025C_1v80,0.31707742884330636
-timing__setup__ws__corner:max_tt_025C_1v80,11.193837285042775
+timing__setup__ws__corner:max_tt_025C_1v80,2.4032061465501093
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -215,7 +215,7 @@ timing__hold_vio__count__corner:max_tt_025C_1v80,0
 timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.317077
 timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
+timing__setup_r2r__ws__corner:max_tt_025C_1v80,2.403206
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__unannotated_net__count__corner:max_tt_025C_1v80,74
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
@@ -224,17 +224,17 @@ design__max_fanout_violation__count__corner:max_ss_100C_1v60,13
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.2791421339752791
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.27686922982383316
-timing__hold__ws__corner:max_ss_100C_1v60,0.8520560054241058
-timing__setup__ws__corner:max_ss_100C_1v60,9.111396339750016
+timing__hold__ws__corner:max_ss_100C_1v60,0.7371454766348562
+timing__setup__ws__corner:max_ss_100C_1v60,1.8703839006998735
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
 timing__setup__wns__corner:max_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:max_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.852056
+timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.737145
 timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:max_ss_100C_1v60,12.182004
+timing__setup_r2r__ws__corner:max_ss_100C_1v60,1.870384
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,74
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
@@ -244,7 +244,7 @@ design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.2695349575378539
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.2660333140191529
 timing__hold__ws__corner:max_ff_n40C_1v95,0.12029316772061992
-timing__setup__ws__corner:max_ff_n40C_1v95,11.373882602127477
+timing__setup__ws__corner:max_ff_n40C_1v95,2.573211272449959
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -253,7 +253,7 @@ timing__hold_vio__count__corner:max_ff_n40C_1v95,0
 timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.120293
 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
+timing__setup_r2r__ws__corner:max_ff_n40C_1v95,2.573211
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:max_ff_n40C_1v95,74
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0