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htfab
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ci(gds): apply platform update from Krzysztof
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‎.github/workflows/gds.yaml

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@@ -43,6 +43,13 @@ jobs:
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submodules: recursive
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path: 'orfs'
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- name: Apply platform update
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run: |
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export UPDATE_DIR=$(realpath sg13g2-update)
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cd orfs/flow/platforms/ihp-sg13g2
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python $UPDATE_DIR/sg13g2-update.py
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cp $UPDATE_DIR/config.mk .
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- name: Run the flow
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working-directory: 'orfs/flow'
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env:

‎designs/ihp-sg13g2/tt-chip/config.mk

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@@ -48,5 +48,3 @@ export ADDITIONAL_GDS = \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/bondpad/gds/bondpad_70x70.gds
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export ADDITIONAL_LIBS = \
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$(IHP_PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_io/liberty/sg13g2_io_dummy.lib
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export GDS_LAYER_MAP = \
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$(PLATFORM_DIR)/sg13g2.map

‎sg13g2-update/config.mk

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# Process node
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export PROCESS = ihp-sg13g2
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#-----------------------------------------------------
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# Tech/Libs
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# ----------------------------------------------------
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export TECH_LEF = $(PLATFORM_DIR)/lef/sg13g2_tech.lef
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export SC_LEF = $(PLATFORM_DIR)/lef/sg13g2_stdcell.lef
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export LIB_FILES = $(PLATFORM_DIR)/lib/sg13g2_stdcell_typ_1p20V_25C.lib \
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$(ADDITIONAL_LIBS)
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export GDS_FILES = $(PLATFORM_DIR)/gds/sg13g2_stdcell.gds \
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$(ADDITIONAL_GDS)
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# Dont use cells to ease congestion
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# Specify at least one filler cell if none
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# The *probe* are for inserting probe points and have metal shapes
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# on all layers.
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# *lpflow* cells are for multi-power domains
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export DONT_USE_CELLS += \
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sg13g2_lgcp_1 \
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sg13g2_sighold \
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sg13g2_slgcp_1 \
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sg13g2_dfrbp_2
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# Define fill cells
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export FILL_CELLS = sg13g2_fill_1 sg13g2_fill_2 sg13g2_decap_4 sg13g2_decap_8
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# -----------------------------------------------------
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# Yosys
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# ----------------------------------------------------
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# Set the TIEHI/TIELO cells
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# These are used in yosys synthesis to avoid logical 1/0's in the netlist
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export TIEHI_CELL_AND_PORT = sg13g2_tiehi L_HI
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export TIELO_CELL_AND_PORT = sg13g2_tielo L_LO
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# Used in synthesis
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export MIN_BUF_CELL_AND_PORTS = sg13g2_buf_1 A X
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# Yosys mapping files
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export LATCH_MAP_FILE = $(PLATFORM_DIR)/cells_latch.v
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export CLKGATE_MAP_FILE = $(PLATFORM_DIR)/cells_clkgate.v
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# Define ABC driver and load
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export ABC_DRIVER_CELL = sg13g2_buf_4
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export ABC_LOAD_IN_FF = 6.0
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# Set yosys-abc clock period to first "clk_period" value or "-period" value found in sdc file
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export ABC_CLOCK_PERIOD_IN_PS ?= $(shell sed -nE "s/^set clk_period (.+)|.* -period (.+) .*/\1\2/p" $(SDC_FILE) | head -1 | awk '{print $$1*1000}')
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#--------------------------------------------------------
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# Floorplan
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# -------------------------------------------------------
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# Placement site for core cells
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# This can be found in the technology lef
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export PLACE_SITE = CoreSite
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# IO Placer pin layers
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export IO_PLACER_H = Metal2
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export IO_PLACER_V = Metal3
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# Define default PDN config
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export PDN_TCL ?= $(PLATFORM_DIR)/pdn.tcl
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# There are no Endcap and Welltie cells in this PDK, so
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# `cut_rows` has to be called from the tapcell script.
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export TAPCELL_TCL = $(PLATFORM_DIR)/tapcell.tcl
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export MACRO_PLACE_HALO ?= 40 40
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export MACRO_PLACE_CHANNEL ?= 80 80
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#---------------------------------------------------------
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# Place
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# --------------------------------------------------------
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# default cell padding for cells
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export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT ?= 2
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export CELL_PAD_IN_SITES_DETAIL_PLACEMENT ?= 1
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export PLACE_DENSITY ?= 0.65
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# --------------------------------------------------------
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# CTS
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# -------------------------------------------------------
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# TritonCTS options
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export CTS_BUF_CELL ?= sg13g2_buf_2
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# ---------------------------------------------------------
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# Route
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# ---------------------------------------------------------
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# FastRoute options
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export MIN_ROUTING_LAYER ?= Metal2
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export MAX_ROUTING_LAYER ?= Metal5
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#export VIA_IN_PIN_MIN_LAYER ?= Metal1
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#export VIA_IN_PIN_MAX_LAYER ?= Metal1
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#export DISABLE_VIA_GEN ?= 1
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#
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# Define fastRoute tcl
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export FASTROUTE_TCL ?= $(PLATFORM_DIR)/fastroute.tcl
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# KLayout technology file
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export KLAYOUT_TECH_FILE = $(PLATFORM_DIR)/sg13g2.lyt
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#
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# Rules for metal fill
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export FILL_CONFIG = $(PLATFORM_DIR)/fill.json
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#
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# Template definition for power grid analysis
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#export TEMPLATE_PGA_CFG ?= $(PLATFORM_DIR)/template_pga.cfg
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# OpenRCX extRules
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export RCX_RULES = $(PLATFORM_DIR)/rcx_patterns.rules
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# GDS streaming
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#
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export GDS_LAYER_MAP = $(PLATFORM_DIR)/sg13g2.map
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# ---------------------------------------------------------
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# IR Drop
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# ---------------------------------------------------------
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# IR drop estimation supply net name to be analyzed and supply voltage variable
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# For multiple nets: PWR_NETS_VOLTAGES = "VDD1 1.8 VDD2 1.2"
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export PWR_NETS_VOLTAGES ?= "VDD 1.2"
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export GND_NETS_VOLTAGES ?= "VSS 0.0"
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export IR_DROP_LAYER ?= Metal1
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# DRC Check
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export KLAYOUT_DRC_FILE = $(PLATFORM_DIR)/drc/sg13g2_minimal.lydrc
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#LVS Check
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export CDL_FILE = $(PLATFORM_DIR)/cdl/sg13g2_stdcell.cdl
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#export KLAYOUT_LVS_FILE = $(PLATFORM_DIR)/lvs/$(PLATFORM).lylvs

‎sg13g2-update/sg13g2-update.py

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import requests
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import os
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def download_github_file(repo_owner, repo_name, branch, file_path, local_dir):
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"""
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Download a file from a specific branch of a GitHub repository.
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Args:
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repo_owner (str): Owner of the repository.
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repo_name (str): Name of the repository.
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branch (str): Branch name from which to download the file.
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file_path (str): Path to the file in the repository.
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local_dir (str): Local directory to save the file.
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Returns:
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None
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"""
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# Construct the URL to access the file
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base_url = f"https://raw.githubusercontent.com/{repo_owner}/{repo_name}/{branch}/{file_path}"
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# Send a GET request to download the file
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response = requests.get(base_url)
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response.raise_for_status() # Raise an exception for HTTP errors
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# Ensure the local directory exists
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if not os.path.exists(local_dir):
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os.makedirs(local_dir)
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# Define the local path to save the file
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local_file_path = os.path.join(local_dir, os.path.basename(file_path))
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# Write the content to the file
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with open(local_file_path, 'wb') as file:
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file.write(response.content)
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print(f"File saved to {local_file_path}")
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owner= 'IHP-GmbH'
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repo_name= 'IHP-Open-PDK'
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branch = 'dev'
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# Klayout
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp', '.')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt', '.')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc', 'drc')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_minimal.lydrc', 'drc')
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# LIB
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p35V_125C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p32V_m40C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_fast_1p65V_m40C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p20V_25C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_typ_1p50V_25C.lib', 'lib')
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# wait for official update
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_dummy.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_fast_1p65V_3p6V_m40C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p35V_3p0V_125C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib', 'lib')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_typ_1p5V_3p3V_25C.lib', 'lib')
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# GDS
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/gds/sg13g2_stdcell.gds', 'gds')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/gds/sg13g2_io.gds', 'gds')
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# LEF
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef', 'lef')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef', 'lef')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef', 'lef')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io_notracks.lef', 'lef')
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# Verilog
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v', 'verilog')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v', 'verilog')
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# CDL
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_stdcell/cdl/sg13g2_stdcell.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_io/cdl/sg13g2_io.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x64_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_1024x64_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_2048x64_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_256x48_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_256x64_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_512x64_c2_bm_bist.cdl', 'cdl')
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download_github_file(owner, repo_name, branch, 'ihp-sg13g2/libs.ref/sg13g2_sram/cdl/RM_IHPSG13_1P_64x64_c2_bm_bist.cdl', 'cdl')

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