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Pull requests: UCSBarchlab/PyRTL

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Pull requests list

Migrate PyRTL to uv
#476 opened Oct 31, 2025 by fdxmw Loading…
2
Pyrtl floating point library
#475 opened Oct 30, 2025 by gaborszita • Draft
16
Allow passing custom module name to output_to_verilog
#474 opened Oct 21, 2025 by devmam999 Loading…
33
Add Posit Support to PyRTL
#473 opened Oct 6, 2025 by arvindajaybharadwaj Loading…
@fdxmw
5
Throw an exception if the user tries to render a trace without stepping the simulation
#472 opened Sep 7, 2025 by gaborszita Loading…
2
Added Module name change functionality for Issue #420
#427 opened Sep 27, 2022 by spencercheese Loading…
Implement a language agnostic hardware representation
#404 opened Sep 21, 2021 by RhysGretsch81 Loading…
4
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
#398 opened Jul 9, 2021 by mdko Loading…
1
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