risc-v

UTOSS' starter multicycle RISC-V core.

Getting Started

Checkout Setting up Developement Environment wiki page.

Project structure

.
├── src -------------------------- contains core's source modules
│   └── utoss_riscv.sv ----------- our core's top module
├── test ------------------------- contains our SystemVerilog testbenches
│   └── vcd ---------------------- contains VCD file outputs generated by the testbenches
├── out -------------------------- contains .vvp builds for testbenches and core module
├── riscof ----------------------- contains RISCOF-related files and scripts; we use this framework
│                                  for compiance testing, to make sure our core behaves as defined
│                                  by the ISA specification; check out the corresponding wiki page
│                                  here for more details:
├── envs ------------------------- contains execution environments to connect our core to platforms
|   |                              for simulation and testing
│   ├── de1-soc ------------------ one of the platforms we support; DE1-SoC is an FPGA board with a
│   │                              bunch of peritherals commonly used for digital design courses at
│   │                              the University of Toronto; check-out corresponding wiki page here
|   |                              for more details:
│   └── simulation --------------- abstract platform implementation we use for testing
│       ├── MA.sv ---------------- memory peripheral implementation
│       └── top.sv --------------- instantiates our core and its peripherals
├── Makefile --------------------- top-level build targets/scripts declarations
├── README.md -------------------- this file
├── svlint.toml ------------------ project-wide config for linting SystemVerilog code
├── Dockerfile.ci ---------------- image for CI pipeline with all necessary dependencies
└── Dockerfile.riscv-toolchain --- sidekick image that builds RISC-V toolchain from source

Development

Put new modules into src/ folder.

Formatting

We use SVLint to make sure our SystemVerilog code is well formatted. Use the following command to check for new offences:

$ make svlint

Testbenches

It is important that new functionality is tested to a reasonable extent by using test benches. To run all existing testbenches use make run_tb

To create a new test bench, if you are on Linux use the following command:

$ make new_tb name="something"

If you are on Windows, create a new testbench file in test/ folder named something_tb.sv (the _tb.sv suffix and extension are necessary for the test suite to recognize this file as a testbench). Copy the content of test/tb_template.sv.m4 into your newly-created testbench file and start writing the test bench.