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Labels
Core: AXI4-Lite Register
Core: AXI4-Lite Version Register
Enhancement
Code improvements.
PoC.mem.*
Memory implementations.
PoC.misc.*
Miscellaneous components.
PoC.xil.*
Xilinx specific components.
Release Plan
Planning issue for an upcoming release.
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New Features
axi4lite_VersionRegistermodule and necessary files:axi4lite_GitVersionRegistermem_GitVersionRegistertools/git/preSynth_GitVersionRegister_Vivado.tclxil_DNAPortsync_Bitsfor CDC infifo_ic_got(code reruse and apply constraints automatically).fifo_shiftcomm_crcT_FRACTIONALlist_expiremisc_Sequencermisc_StrobeGeneratormisc_StrobeLimitermisc_StrobeStretchermac_TX_Type_PrependerChanges
downcounter; changed Init value's type anatural.my_configtemplate withGENERICas device exampleBug Fixes
bus_Arbiter: Throw failure when unimplemented lottery strategy is selected.*.profiles for analyzing in simulators:arith_scaler: Initialize arrays with'0'instead of'-'for better/easier simulationremote_terminal_control: Fix package nameDocumentation
Tests
axi4lite_Register(see Updated AXI4Lite register testcase #20)Clean-Up
*.files, since they are outdated and the compile order is now defined by the*.profiles usable with OSVVM-Scripting.sim/obsoleted by OSVVMRelated Issues and Pull-Requests