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@Paebbels Paebbels commented Aug 27, 2025

New Features

  • Added axi4lite_VersionRegister module and necessary files:
    • Entity axi4lite_GitVersionRegister
    • Package mem_GitVersionRegister
    • Synthesis pre-TCL script tools/git/preSynth_GitVersionRegister_Vivado.tcl
    • Entity xil_DNAPort
  • Use sync_Bits for CDC in fifo_ic_got (code reruse and apply constraints automatically).
  • Added empty/fill-level output for fifo_shift
  • Add chunk-enable feature for comm_crc
  • Support for fraction of one for type T_FRACTIONAL
  • Entity list_expire
  • Entity misc_Sequencer
  • Entity misc_StrobeGenerator
  • Entity misc_StrobeLimiter
  • Entity misc_StrobeStretcher
  • Entity mac_TX_Type_Prepender

Changes

  • Check if Init value fits in downcounter; changed Init value's type a natural.
  • Updated my_config template with GENERIC as device example

Bug Fixes

  • bus_Arbiter: Throw failure when unimplemented lottery strategy is selected.
  • Added missing VHDL sources to *.pro files for analyzing in simulators:
    • syntax check
    • instantiation check
  • arith_scaler: Initialize arrays with '0' instead of '-' for better/easier simulation
  • remote_terminal_control: Fix package name

Documentation

  • tbd
  • tbd

Tests

  • Run simulations additionally with GHDL mcode backend and NVC for better simulation coverage.
  • axi4lite_Register (see Updated AXI4Lite register testcase #20)
    • updated register definition
    • added testcase for
      • checking initial values on all registers
      • simple read write

Clean-Up

  • Remove all *.files, since they are outdated and the compile order is now defined by the *.pro files usable with OSVVM-Scripting.
  • Remove old and unused VHDL files
    • sim/ obsoleted by OSVVM
    • Xilinx ISE related files

Related Issues and Pull-Requests


Co-authored-by: Adrian Weiland <[email protected]>
Co-authored-by: Asif Iqbal <[email protected]>
Co-authored-by: Max Kraft-Kugler <[email protected]>
Co-authored-by: Jonas Schreiner <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>
Co-authored-by: Patrick Lehmann <[email protected]>

@Paebbels Paebbels force-pushed the dev branch 2 times, most recently from 02847ce to f83392f Compare August 30, 2025 21:49
@Paebbels Paebbels force-pushed the dev branch 4 times, most recently from 6504e67 to 3d13d5b Compare September 9, 2025 15:00
@Paebbels Paebbels force-pushed the dev branch 4 times, most recently from 859cd5f to 3e2ae29 Compare September 13, 2025 09:46
@Paebbels Paebbels force-pushed the dev branch 3 times, most recently from 6030e51 to 68e1204 Compare October 7, 2025 05:46
@Paebbels Paebbels marked this pull request as ready for review October 13, 2025 07:29
@Paebbels Paebbels merged commit a43c64a into master Oct 13, 2025
36 of 38 checks passed
@Paebbels Paebbels deleted the dev branch October 13, 2025 07:29
@Paebbels Paebbels added Release Plan Planning issue for an upcoming release. Core: AXI4-Lite Register Core: AXI4-Lite Version Register PoC.misc.* Miscellaneous components. PoC.mem.* Memory implementations. PoC.xil.* Xilinx specific components. labels Nov 28, 2025
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Labels

Core: AXI4-Lite Register Core: AXI4-Lite Version Register Enhancement Code improvements. PoC.mem.* Memory implementations. PoC.misc.* Miscellaneous components. PoC.xil.* Xilinx specific components. Release Plan Planning issue for an upcoming release.

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4 participants