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VHDL / PoC Public

forked from VLSI-EDA/PoC

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Fork 6
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Issues 8
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Feature/axi4 l register interface update#29

Open

stefanunrein wants to merge 5 commits intoVHDL:devVHDL/PoC:devfrom

PLC2:feature/AXI4L-register_interface_updatePLC2/PoC:feature/AXI4L-register_interface_updateCopy head branch name to clipboard

Conversation Commits5 (5)Checks Files changed

Open

Feature/axi4 l register interface update#29
stefanunrein wants to merge 5 commits intoVHDL:devfrom
PLC2:feature/AXI4L-register_interface_update

Commits

Commits on Nov 23, 2025

Add output port for GitVersionRegister with its register content as records
stefanunrein
committed
Add missing sources to TerosHDL project file
stefanunrein
committed

Commits on Nov 24, 2025

fix function declaration
stefanunrein
committed
create function for reading mem-content directly into record-constant
stefanunrein
committed
Add description for constant usage
stefanunrein
committed

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