Dynamic bsg_fakeram

Makefile

@@ -7,13 +7,13 @@ CONFIG := $(TOP_DIR)/example_cfgs/freepdk45.cfg
 OUT_DIR := $(TOP_DIR)/results
 
 run:
-	./scripts/run.py $(CONFIG) --output_dir $(OUT_DIR)
+	PYTHONDONTWRITEBYTECODE=1 ./scripts/run.py $(CONFIG) --output_dir $(OUT_DIR)
 
 view.%:
 	klayout ./$(OUT_DIR)/$*/$*.lef &
 
 clean:
-	rm -rf $(OUT_DIR)
+	rm -rf ./$(OUT_DIR)
 
 #=======================================
 # TOOLS
@@ -32,3 +32,5 @@ $(CACTI_BUILD_DIR):
 clean_tools:
 	rm -rf $(CACTI_BUILD_DIR)
 
+test:
+	bash ./scripts/tests/run_test.sh

README.md

@@ -15,30 +15,51 @@ $ make tools
 
 ## Usage
 
-### Configuration File
+### Process Configuration
 
 The input to the BSG Black-box SRAM generator is a simple JSON file that
 contains some information about the technology node you are targeting as well
 as the size and names of SRAMs you would like to generate. Below is an example
-JSON file that can be found in `./example_cfgs/freepdk45.cfg`:
+JSON file that can be found in `./example_cfgs/asap7.cfg`:
 
 ```
 {
-  "tech_nm": 45,
-  "voltage": 1.1,
-  "metalPrefix": "metal",
-  "pinWidth_nm": 70,
-  "pinPitch_nm": 140,
-  "snapWidth_nm": 190,
-  "snapHeight_nm": 1400,
-  "flipPins": True,
+  "custom_tech_name": "asap7",
+  "hybrid": false,
+  "column_mux_factor": 4,
+  "tech_nm": 7,
+  "voltage": 0.7,
+  "metalPrefix": "M",
+  "metal_layer": "M4",
+  "pinWidth_nm": 24,
+  "pinPitch_nm": 48,
+  "manufacturing_grid_nm": 1,
+  "snap_width_nm": 190,
+  "snap_height_nm": 1400,
+  "flipPins": "false",
   "srams": [
-    {"name": "sram_32x32_1rw", "width": 32, "depth":  32, "banks": 1},
-    {"name": "sram_8x512_1rw", "width":  8, "depth": 512, "banks": 1}
+    {
+      "name": "testram_1w_64w256d_16_sram",
+      "width": 64,
+      "depth": 256,
+      "banks": 1,
+      "column_mux_factor_override": 2,
+      "write_mode": "write_first",
+      "write_granularity": 16,
+      "r": 0,
+      "w": [1, "left"],
+      "rw": 0
+    }
   ]
 }
 ```
 
+`custom_tech_name` - Name of the custom tech yml file
+
+`hybrid` - (Optional : False) Overrides specific cacti values with values in yml file. Otherwise will use cacti as default.
+
+`column_mux_factor` - (Optional : 1) It reduces the number of sense amplifiers needed, saving area, but may increase access time. When used the height is divided by its column mux factor and width multiplied by its column mux factor for all srams. Column mux factor defaults to 1. Can be overriden for a specific sram with parameter column_mux_factor_override in "sram". If CACTI is ran, this is ignored.
+
 `tech_nm` - The name of the target technology node (in nm). Used in Cacti for
 modeling PPA of the SRAM.
 
@@ -64,9 +85,51 @@ supply straps (also on metal 4) will be horizontal. If set to true then metal 1
 is assumed to be horizontal. This means that signal pins will be on metal 3 and
 the supply straps (on metal 4) will be vertical.
 
+`manufacturing_grid_nm` - The manufacturing grid for specific technology (in nm).
+
+### Memory Configuration
+
 `srams` - A list of SRAMs to generate. Each sram should have a `name`, `width`
 (or the number of bits per word), `depth` (or number of words), and `banks`.
 
+`column_mux_factor_override` - ( Optional : column_mux_factor value ) Overrides column_mux_factor for a specific sram.
+
+`write_mode` - ( Optional : write_first ) For Read Write ports, optional to chose as read_first otherwise write_first.
+
+`write_granularity` -  Specifies number of bits that can be written in a single write operation.
+
+`Ports` - ( Optional : Left ) Index one specifies number of ports, index two specifies which side port will be placed on. Defaults to left.
+`r` -  [1, "right"],
+`w` -  [1, "right"],
+`rw` -  [1, "left"]
+
+### Porting new tech
+
+Creating a yml file would be optimimal since cacti does not support below 28nm.
+YML file that can be found in `./tech/asap7.cfg`:
+```
+t_setup_ns: 0.050
+t_hold_ns: 0.050
+access_time_ns: 0.2183
+cycle_time_ns: 0.2566
+fo4_ps: 9.0632
+standby_leakage_per_bank_mW: 0.1289
+pin_dynamic_power_mW: 0.0013449
+cap_input_pf: 0.005
+contacted_poly_pitch_nm: 54
+finPitch_nm: 27
+H0_TRACKS: 10
+W0_POLYS: 2
+
+// Optional : Default to 1
+DH_READ: 2
+DW_READ: 0.5
+DH_WRITE: 2.5
+DW_WRITE: 0.5
+DH_RW: 1
+DW_RW: 0.5
+
+```
 
 ### Running the Generator
 

example_cfgs/asap7.cfg

@@ -1,48 +1,208 @@
-# ABKGroup's FakeRAM2.0 config, added to allow dynamic RAM generation of asap7 tech
-
 {
-  # The process node.
+
   "tech_nm": 7,
 
-  # The operating voltage.
   "voltage": 0.7,
 
-  # String to add in front of every metal layer number for the layer name.
   "metalPrefix": "M",
-
-  # The pin width for signal pins.
-  "pinWidth_nm": 24,
 
-  # The minimum pin pitch for signal pins 
-  "pinPitch_nm": 48,
+  "manufacturing_grid_nm": 1,
 
-  # Metal track pitch  
-  "metal_track_pitch_nm": 48, 
+  # Pins
+  "pinParams": {
+    "metLayerHorizontalPin": 3,
+    "metLayerVerticalPin": 4,
 
-  # Manufacturing Grid 
-  "manufacturing_grid_nm": 1,
+    # set 36nm to x track pitch in met3
+    "x_pinPitch_nm": 36,
+
+    # set 48nm to y track pitch in met4
+    "y_pinPitch_nm": 48,
+
+    # pitch + offset
+    "x_pinOffset_nm": 0,
+    "y_pinOffset_nm": 0,
+
+    # Pin dimensions
+    "pinWidth_nm" : 48,
+    "pinHeight_nm": 48
+  },
+
+  # Power Grid
+  "powerGridParams": {
+      # "vertical" or "horizonal" strapes
+      "directionPowerGrid": "horizontal",
+      "metLayerPowerGrid": 4,
+
+      # pinWidth * 4 = 96nm
+      "powerGridWidth_nm": 96,
+
+      # met4 x track pitch * 8 = 384nm 
+      "powerGridPitch_nm": 384
+  },
 
-  # Contacted Poly Pitch
-  "contacted_poly_pitch_nm": 54,
+  # timing for all srams
+  "timing": {
+    "t_setup_ns": 0.050,
+    "t_hold_ns": 0.050,
+    "cap_input_pf": 0.005
+  },
 
-  #column mux factor
-  "column_mux_factor": 1,
+  "additionalParams": {
+    # TODO: heightSnaptoTrack to heightSnaptoNearestPitch 
+    # snap sram dimensions to track (reccomended)
+    # y offset ignored
+    "heightSnapPinPitch": true,
 
-  # Fin pitch
-  "fin_pitch_nm" : 27,
+    # x offset ignored
+    "widthSnapPinPitch": true,
 
-  # Flip Pins = false for M4, true for M3
-  "flipPins": false,
+    # pins will be equidistant throughout all
+    # sides based on snap mode, pitch factor is ignored
+    # TODO:
+    # "equidistantPins": false,
 
-  # Optional snap the width and height of the sram to a multiple value.
-  "snap_width_nm":  190,
-  "snap_height_nm": 1400,
+    # all pins will be placed on left/right sides of sram
+    "verticalPinsOnly": false,
+
+    # column mux factor to all srams unless overriden
+    "column_mux_factor": 4,
+    "snapWidth_nm": 190,
+    "snapHeight_nm": 1400
+  },
+
+  # uses custom_tech, defaults to false
+  "use_custom_tech": true,
+
+  # Custom tech parameters
+  "custom_tech": {
+    # If set to false means the tool will not use CACTI for memory 
+    # modeling; it will use only the values provided in "custom_tech".
+    # If set to true, the tool would run CACTI and then override any CACTI
+    # generated values with those specified in "custom_tech".
+    "hybrid": false,
+
+    # REQUIRED PARAMS / OPTIONAL hybrid cacti override
+    # params here would only be overrided by cacti
+    "access_time_ns": 0.2183,
+    "cycle_time_ns": 0.2566,
+    "fo4_ps": 9.0632,
+    "standby_leakage_per_bank_mW": 0.1289,
+    "pin_dynamic_power_mW": 0.0013449,
+
+    # NON-HYBRID REQUIRED PARAMS
+    "finPitch_nm": 27,
+    "contacted_poly_pitch_nm": 54,
+
+    # Needed tracks/poly for asap7 122 sram cell
+    # 10 fin pitches
+    "h0_tracks": 10,
+    "w0_polys": 2,
+
+    # OPTIONAL VARIABLES (Ignored with hybrid)
+    # Optional overhead, default: 1
+    "dh_read": 2,
+    "dw_read": 0.5,
+    "dh_write": 2.5,
+    "dw_write": 0.5,
+    "dh_rw": 1,
+    "dw_rw": 0.5
+
+  },
 
-
   # List of SRAM configurations (name width depth and banks)
   "srams": [ 
-    {"name": "fakeram7_64x21", "width": 21, "depth": 64, "banks": 2, "ports": "1rw", "port_clks": "[0], [], []"},
-    {"name": "fakeram7_256x34", "width": 34, "depth": 256, "banks": 2, "ports": "1rw", "port_clks": "[0], [], []"},
-    {"name": "fakeram7_2048x39", "width": 39, "depth": 2048, "banks": 4, "ports": "1rw", "port_clks": "[0], [], []"}
-  ] 
-}
+    {"name": "testram_1rw_39w2048d_sram", 
+     "width": 39,
+     "depth": 2048,
+     "banks": 2,
+     "pinPitchFactor": 6,
+     "column_mux_factor_override": 3,
+     "write_mode": "write_first",
+     "ports": {
+     "r": 0,
+     "w": 0,
+     "rw": 1
+     }
+    },
+
+    {"name": "testram_1w_64w256d_16_sram", 
+     "width": 64,
+     "depth": 256,
+     "banks": 1,
+     "pinPitchFactor": 5,
+     "column_mux_factor_override": 2,
+     "write_mode": "write_first",
+     "write_granularity": 16,
+     "ports": {
+     "r": 0,
+     "w": 1,
+     "rw": 0
+     }
+    },
+    {"name": "testram_2rw_32w1024d_sram", 
+     "width": 32,
+     "depth": 1024,
+     "banks": 1,
+     "pinPitchFactor": 3,
+     "write_mode": "read_first",
+     "ports": {
+     "r": 0,
+     "w": 0,
+     "rw": 2
+     }
+    },
+    {"name": "testram_1r1w_8w64d_4_sram", 
+     "width": 8,
+     "depth": 64,
+     "banks": 1,
+     "pinPitchFactor": 1,
+     "write_mode": "write_first",
+     "write_granularity": 4,
+     "ports": {
+     "r": 1,
+     "w": 1,
+     "rw": 0
+     }
+    },
+    {"name": "testram_2r_24w512d_sram", 
+     "width": 24,
+     "depth": 512,
+     "banks": 1,
+     "pinPitchFactor": 3,
+     "write_mode": "read_first",
+     "ports": {
+     "r": 2,
+     "w": 0,
+     "rw": 0
+     }
+    },
+    {"name": "testram_1r2w_48w1024d_8_sram", 
+     "width": 48,
+     "depth": 1024,
+     "banks": 2,
+     "pinPitchFactor": 7,
+     "write_mode": "read_first",
+     "write_granularity": 8,
+     "ports": {
+     "r": 1,
+     "w": 2,
+     "rw": 0
+     }
+    },
+    {"name": "testram_2r2w_90w2048d_18_sram", 
+     "width": 90,
+     "depth": 2048,
+     "banks": 2,
+     "pinPitchFactor": 10,
+     "write_mode": "read_first",
+     "column_mux_factor_override": 3,
+     "write_granularity": 18,
+     "ports": {
+     "r": 2,
+     "w": 2,
+     "rw": 0
+     }
+    }
+  ]
+}