phy: use comb logic for clk div, when provided by core

use comb logic for clk div, when provided by core,
so it can directly be used, when it's avalible.
NEeded due to the change of start of the cs timer.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

litespi/phy/generic_ddr_with_clk.py

@@ -91,12 +91,16 @@ def __init__(self, pads, flash, clock_domain, default_divisor=9, extra_latency=0
         # CS control.
         self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, **kwargs)
 
+        spi_clk_divisor_delayed = Signal(len(sink.clk_div))
+
         # Only Clk Divisor when not active or when set by core.
-        self.sync += [
+        self.sync += If(~clkgen.en, spi_clk_divisor_delayed.eq(spi_clk_divisor))
+
+        self.comb += [
             If(sink.valid & (sink.clk_div > 0),
                 clkgen.div.eq(sink.clk_div),
-            ).Elif(~cs_control.enable,
-                clkgen.div.eq(spi_clk_divisor),
+            ).Else(
+                clkgen.div.eq(spi_clk_divisor_delayed),
             )
         ]
 

litespi/phy/generic_sdr.py

@@ -92,12 +92,16 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor=9, extra_l
         # CS control.
         self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, **kwargs)
 
+        spi_clk_divisor_delayed = Signal(len(sink.clk_div))
+
         # Only Clk Divisor when not active or when set by core.
-        self.sync += [
+        self.sync += If(~clkgen.en, spi_clk_divisor_delayed.eq(spi_clk_divisor))
+
+        self.comb += [
             If(sink.valid & (sink.clk_div > 0),
                 clkgen.div.eq(sink.clk_div),
-            ).Elif(~cs_control.enable,
-                clkgen.div.eq(spi_clk_divisor),
+            ).Else(
+                clkgen.div.eq(spi_clk_divisor_delayed),
             )
         ]