fpga_lcd_driver

FPGA to control the lcd This project allows you to drive an lcd display without driver, with any FPGA. I'm using Tang nano 1k FPGA and 525x286 tft lcd for this project.

Prerequisites

1. Check whether your FPGA have FPC connector provision. In Tang nano 1k, a 40pin FPC connecter is available. Else you need to have a breakout board with FPC connector.
2. Choose the lcd wisely. LCD pins must have same number of pins as that of the FPC. In LCD flex cable and FPGA FPC, first pin mentioned as '1'. Proper connection is important.
3. Mostly the lcds are made for RGB888 protocol which is 8 bits per each color. RGB888 allows mode color spectrum but requires more resources of FPGA. Tang nano 1k allows RGB585.

Project overview

1. FPGA : Tang nano 1k(1152LUT)
2. Display : TFT 525x286 pixels(480x272 active pixels) RGB565 Color depth
3. Clock : 27Mhz(FPGA),9Mhz (Display)
4. Disply refreshrate : 60Hz

Timing specification

1. Active Display : 480(Horizontal pixels) ,272(Vertical lines) ,
2. Front Porch : 2(For Hsync and Vsync),
3. Sync Pulse : 41(Hsync),10(Vsync),
4. Back Porch : 2(For Hsync and Vsync),
5. Total Frame : 525(Horizontal pixels), 286(Vertical lines)

What does it means

One pixel contains 3 leds(Red,Green,Blue). Each led takes 8 bits of data. In RGB565, R and B takes 5 MSB out of 8 bits while G take 6 MSB out of 8 bits. Rest are assumed 0 bits. There are total 286 vertical lines in which each vertical line have 525 pixels. For each pixel, one complete display clock is needed. One vsync stands for completeion of 286 lines while one hsync stands for 525 pixels. So in one frame vsync cycles only once and hsync cycles for 286 times. Literally there are 525x286 pixels in one frame. But we cant use all those pixels. Instead we are allowed to use only 480x272 pixels for each frame by avoiding front porch, back porch and pulse width. These are called blanking area where nothing is displayed.

Repo structure

1. src/ : Source files
2. cst/ : Constraints file
3. docs/ : Required documents

Building the project

1. Clone the repo https://github.com/VSSR-01/fpga_lcd_driver.git
2. Open GowinEDA tool a. Create project for your FPGA b. Copy source files to src folder in your project folder c. Copy constraints (.cst) to the constraints folder
3. Synthesize, Place and route and program the .fs file into the FPGA.

Tools Required

1. Gowin EDA(You can use OSS CAD SUITE also)
2. Icarus Verilog compiler for simulation
3. gtkwave for visualising the signal waveform

Note

Any FPGA can be used for this purpose as long as there are sufficient LUTS and pins available. Proprietary EDA tools and open source tools are available for most FPGAs. FPGAs have pLL IPs available to create specific frequency than the available board frequency. It is better to use IPs instead of creating a clock divider from the available clock.