Add support for non-byte tdata widths in AXI stream VCs.

This is non-standard and must explicitly be enabled. The difference from
the standard implementation is with respect to the length of tkeep and
tstrb which is calculated as (tdata'length + 7) / 8 rather than tdata'length / 8 .

Author: LarsAsplund

docs/news.d/1127.feature.rst

@@ -0,0 +1,3 @@
+The AXI stream standard requires tdata to be a multiple of 8 bits. Updated AXI stream VCs to also support other bit widths.
+This affects tkeep and tstrb which widths are set to (tdata'length + 7) / 8 rather than tdata'length / 8. This new feature
+is disabled by default and is enabled by setting the allow_arbitrary_data_length to true in the VC constructor call.

vunit/vhdl/verification_components/run.py

@@ -134,7 +134,7 @@ def gen_avalon_master_tests(obj, *args):
 for id_length in [0, 8]:
     for dest_length in [0, 8]:
         for user_length in [0, 8]:
-            for data_length in [8, 16]:
+            for data_length in [3, 8, 11, 16]:
                 for test in TB_AXI_STREAM.get_tests("*check"):
                     test.add_config(
                         name=f"id_l={id_length} dest_l={dest_length} user_l={user_length} data_l={data_length}",
@@ -150,7 +150,7 @@ def gen_avalon_master_tests(obj, *args):
 
 TB_AXI_STREAM_PROTOCOL_CHECKER = LIB.test_bench("tb_axi_stream_protocol_checker")
 
-for data_length in [0, 8, 32]:
+for data_length in [0, 3, 8, 11, 32]:
     for test in TB_AXI_STREAM_PROTOCOL_CHECKER.get_tests("*passing*tdata*"):
         test.add_config(name="data_length=%d" % data_length, generics=dict(data_length=data_length))
 

vunit/vhdl/verification_components/src/axi_stream_master.vhd

@@ -37,8 +37,8 @@ entity axi_stream_master is
     tready       : in  std_logic                                          := '1';
     tdata        : out std_logic_vector(data_length(master)-1 downto 0)   := (others => '0');
     tlast        : out std_logic                                          := '0';
-    tkeep        : out std_logic_vector(data_length(master)/8-1 downto 0) := (others => '1');
-    tstrb        : out std_logic_vector(data_length(master)/8-1 downto 0) := (others => '1');
+    tkeep        : out std_logic_vector(keep_strb_length(master)-1 downto 0) := (others => '1');
+    tstrb        : out std_logic_vector(keep_strb_length(master)-1 downto 0) := (others => '1');
     tid          : out std_logic_vector(id_length(master)-1 downto 0)     := (others => '0');
     tdest        : out std_logic_vector(dest_length(master)-1 downto 0)   := (others => '0');
     tuser        : out std_logic_vector(user_length(master)-1 downto 0)   := (others => '0')
@@ -55,8 +55,8 @@ architecture a of axi_stream_master is
 
 
   procedure drive_invalid_output(signal l_tdata : out std_logic_vector(data_length(master)-1 downto 0);
-                                 signal l_tkeep : out std_logic_vector(data_length(master)/8-1 downto 0);
-                                 signal l_tstrb : out std_logic_vector(data_length(master)/8-1 downto 0);
+                                 signal l_tkeep : out std_logic_vector(keep_strb_length(master)-1 downto 0);
+                                 signal l_tstrb : out std_logic_vector(keep_strb_length(master)-1 downto 0);
                                  signal l_tid   : out std_logic_vector(id_length(master)-1 downto 0);
                                  signal l_tdest : out std_logic_vector(dest_length(master)-1 downto 0);
                                  signal l_tuser : out std_logic_vector(user_length(master)-1 downto 0))

vunit/vhdl/verification_components/src/axi_stream_monitor.vhd

@@ -24,8 +24,8 @@ entity axi_stream_monitor is
     tready : in std_logic := '1';
     tdata  : in std_logic_vector(data_length(monitor) - 1 downto 0);
     tlast  : in std_logic := '1';
-    tkeep  : in std_logic_vector(data_length(monitor)/8-1 downto 0) := (others => '1');
-    tstrb  : in std_logic_vector(data_length(monitor)/8-1 downto 0) := (others => 'U');
+    tkeep  : in std_logic_vector(keep_strb_length(monitor)-1 downto 0) := (others => '1');
+    tstrb  : in std_logic_vector(keep_strb_length(monitor)-1 downto 0) := (others => 'U');
     tid    : in std_logic_vector(id_length(monitor)-1 downto 0) := (others => '0');
     tdest  : in std_logic_vector(dest_length(monitor)-1 downto 0) := (others => '0');
     tuser  : in std_logic_vector(user_length(monitor)-1 downto 0) := (others => '0')

vunit/vhdl/verification_components/src/axi_stream_pkg.vhd

@@ -30,8 +30,8 @@ entity axi_stream_protocol_checker is
     tready   : in std_logic := '1';
     tdata    : in std_logic_vector(data_length(protocol_checker) - 1 downto 0);
     tlast    : in std_logic                                                    := '1';
-    tkeep    : in std_logic_vector(data_length(protocol_checker)/8-1 downto 0) := (others => '1');
-    tstrb    : in std_logic_vector(data_length(protocol_checker)/8-1 downto 0) := (others => 'U');
+    tkeep    : in std_logic_vector(keep_strb_length(protocol_checker)-1 downto 0) := (others => '1');
+    tstrb    : in std_logic_vector(keep_strb_length(protocol_checker)-1 downto 0) := (others => 'U');
     tid      : in std_logic_vector(id_length(protocol_checker)-1 downto 0)     := (others => '0');
     tdest    : in std_logic_vector(dest_length(protocol_checker)-1 downto 0)   := (others => '0');
     tuser    : in std_logic_vector(user_length(protocol_checker)-1 downto 0)   := (others => '0')
@@ -85,7 +85,7 @@ architecture a of axi_stream_protocol_checker is
     ret := data;
     for i in keep'range loop
       if keep(i) = '0' or strb(i) = '0' then
-        ret(i*8+7 downto i*8) := (others => '0');
+        ret(minimum(i*8+7, ret'left) downto i*8) := (others => '0');
       end if;
     end loop;
     return ret;

vunit/vhdl/verification_components/src/axi_stream_protocol_checker.vhd

@@ -34,8 +34,8 @@ entity axi_stream_slave is
     tready   : out std_logic := '0';
     tdata    : in std_logic_vector(data_length(slave)-1 downto 0);
     tlast    : in std_logic                                         := '1';
-    tkeep    : in std_logic_vector(data_length(slave)/8-1 downto 0) := (others => '1');
-    tstrb    : in std_logic_vector(data_length(slave)/8-1 downto 0) := (others => 'U');
+    tkeep    : in std_logic_vector(keep_strb_length(slave)-1 downto 0) := (others => '1');
+    tstrb    : in std_logic_vector(keep_strb_length(slave)-1 downto 0) := (others => 'U');
     tid      : in std_logic_vector(id_length(slave)-1 downto 0)     := (others => '0');
     tdest    : in std_logic_vector(dest_length(slave)-1 downto 0)   := (others => '0');
     tuser    : in std_logic_vector(user_length(slave)-1 downto 0)   := (others => '0')
@@ -146,7 +146,8 @@ begin
             mismatch := false;
             for idx in tkeep'range loop
               if tkeep(idx) and tstrb_resolved(idx) then
-                mismatch := tdata(8 * idx + 7 downto 8 * idx) /= expected_tdata(8 * idx + 7 downto 8 * idx);
+                mismatch := tdata(minimum(8 * idx + 7, tdata'left) downto 8 * idx) /=
+                            expected_tdata(minimum(8 * idx + 7, tdata'left) downto 8 * idx);
                 exit when mismatch;
               end if;
             end loop;

vunit/vhdl/verification_components/src/axi_stream_slave.vhd

@@ -42,29 +42,31 @@ architecture a of tb_axi_stream is
   constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(
     data_length => g_data_length, id_length => g_id_length, dest_length => g_dest_length, user_length => g_user_length,
     stall_config => master_stall_config, logger => get_logger("master"), actor => new_actor("master"),
-    monitor => default_axi_stream_monitor, protocol_checker => default_axi_stream_protocol_checker
+    monitor => default_axi_stream_monitor, protocol_checker => default_axi_stream_protocol_checker,
+    allow_arbitrary_data_length => g_data_length mod 8 /= 0
   );
   constant master_stream : stream_master_t := as_stream(master_axi_stream);
   constant master_sync   : sync_handle_t   := as_sync(master_axi_stream);
 
   constant slave_axi_stream : axi_stream_slave_t := new_axi_stream_slave(
     data_length => g_data_length, id_length => g_id_length, dest_length => g_dest_length, user_length => g_user_length,
     stall_config => slave_stall_config, logger => get_logger("slave"), actor => new_actor("slave"),
-    monitor => default_axi_stream_monitor, protocol_checker => default_axi_stream_protocol_checker
+    monitor => default_axi_stream_monitor, protocol_checker => default_axi_stream_protocol_checker,
+    allow_arbitrary_data_length => g_data_length mod 8 /= 0
   );
   constant slave_stream : stream_slave_t := as_stream(slave_axi_stream);
   constant slave_sync   : sync_handle_t  := as_sync(slave_axi_stream);
 
   constant monitor : axi_stream_monitor_t := new_axi_stream_monitor(
     data_length => g_data_length, id_length => g_id_length, dest_length => g_dest_length, user_length => g_user_length,
     logger => get_logger("monitor"), actor => new_actor("monitor"),
-    protocol_checker => default_axi_stream_protocol_checker
+    protocol_checker => default_axi_stream_protocol_checker,
+    allow_arbitrary_data_length => g_data_length mod 8 /= 0
   );
 
   constant protocol_checker : axi_stream_protocol_checker_t := new_axi_stream_protocol_checker(
     data_length => g_data_length, id_length => g_id_length, dest_length => g_dest_length, user_length => g_user_length,
-    logger      => get_logger("protocol_checker"),
-    max_waits   => 8
+    logger      => get_logger("protocol_checker"), max_waits   => 8, allow_arbitrary_data_length => g_data_length mod 8 /= 0
   );
 
   constant n_monitors : natural := 3;
@@ -75,8 +77,8 @@ architecture a of tb_axi_stream is
   signal tready : std_logic;
   signal tdata : std_logic_vector(data_length(slave_axi_stream)-1 downto 0);
   signal tlast : std_logic;
-  signal tkeep, tkeep_from_master : std_logic_vector(data_length(slave_axi_stream)/8-1 downto 0);
-  signal tstrb, tstrb_from_master : std_logic_vector(data_length(slave_axi_stream)/8-1 downto 0);
+  signal tkeep, tkeep_from_master : std_logic_vector(keep_strb_length(slave_axi_stream)-1 downto 0);
+  signal tstrb, tstrb_from_master : std_logic_vector(keep_strb_length(slave_axi_stream)-1 downto 0);
   signal tid : std_logic_vector(id_length(slave_axi_stream)-1 downto 0);
   signal tdest : std_logic_vector(dest_length(slave_axi_stream)-1 downto 0);
   signal tuser : std_logic_vector(user_length(slave_axi_stream)-1 downto 0);

vunit/vhdl/verification_components/test/tb_axi_stream.vhd

@@ -35,14 +35,15 @@ architecture a of tb_axi_stream_protocol_checker is
   signal tlast    : std_logic := '1';
   signal tdest    : std_logic_vector(dest_length - 1 downto 0) := (others => '0');
   signal tid      : std_logic_vector(id_length - 1 downto 0) := (others => '0');
-  signal tstrb    : std_logic_vector(data_length/8 - 1 downto 0) := (others => '0');
-  signal tkeep    : std_logic_vector(data_length/8 - 1 downto 0) := (others => '0');
+  signal tstrb    : std_logic_vector((data_length + 7) / 8 - 1 downto 0) := (others => '0');
+  signal tkeep    : std_logic_vector((data_length + 7) / 8 - 1 downto 0) := (others => '0');
   signal tuser    : std_logic_vector(user_length - 1 downto 0) := (others => '0');
 
   constant logger           : logger_t                      := get_logger("protocol_checker");
   constant protocol_checker : axi_stream_protocol_checker_t := new_axi_stream_protocol_checker(
     data_length => tdata'length, id_length => tid'length, dest_length => tdest'length, user_length => tuser'length,
-    logger => logger, actor => new_actor("protocol_checker"), max_waits => max_waits, allow_x_in_non_data_bytes => true
+    logger => logger, actor => new_actor("protocol_checker"), max_waits => max_waits, allow_x_in_non_data_bytes => true,
+    allow_arbitrary_data_length => data_length mod 8 /= 0
   );
   constant meta_values      : std_logic_vector(1 to 5)      := "-XWZU";
   constant valid_values     : std_logic_vector(1 to 4)      := "01LH";