Added areset_n signal to axi_master write

Author: DavidMartinPhios

vunit/vhdl/verification_components/src/axi_master.vhd

@@ -230,8 +230,8 @@ begin
         drive_ar_invalid;
 
       elsif is_write(msg_type) then
-        while rnd.Uniform(0.0, 1.0) > axi_master_handle.p_write_high_probability loop
-          wait until rising_edge(aclk);
+        while rnd.Uniform(0.0, 1.0) > axi_master_handle.p_write_high_probability and areset_n = '1' loop
+          wait until rising_edge(aclk) or areset_n = '0';
         end loop;
 
         addr := pop_std_ulogic_vector(request_msg);
@@ -287,7 +287,11 @@ begin
         wlast <= '1' when len = 0 else '0';
 
         while not (w_done and aw_done) loop
-          wait until ((awvalid and awready) = '1' or (wvalid and wready) = '1') and rising_edge(aclk);
+          wait until (((awvalid and awready) = '1' or (wvalid and wready) = '1') and rising_edge(aclk)) or areset_n = '0';
+
+          if areset_n = '0' then 
+            exit;
+          end if;
 
           if (awvalid and awready) = '1' then
             awvalid <= '0';
@@ -319,10 +323,12 @@ begin
 
         end loop;
 
-        push_std_ulogic_vector(request_msg, addr);
-        push_std_ulogic_vector(request_msg, id);
-        push_std_ulogic_vector(request_msg, resp);
-        push(write_reply_queue, request_msg);
+        if areset_n = '1' then 
+          push_std_ulogic_vector(request_msg, addr);
+          push_std_ulogic_vector(request_msg, id);
+          push_std_ulogic_vector(request_msg, resp);
+          push(write_reply_queue, request_msg);
+        end if;
 
       else
         unexpected_msg_type(msg_type);
@@ -417,18 +423,20 @@ begin
 
     bready <= '1';
     wait until (bvalid and bready) = '1' and rising_edge(aclk);
-    bready <= '0';
+    if areset_n = '1' then 
+      bready <= '0';
 
-    request_msg := pop(write_reply_queue);
-    msg_type := message_type(request_msg);
-    addr := pop_std_ulogic_vector(request_msg);
-    id := pop_std_ulogic_vector(request_msg);
-    resp := pop_std_ulogic_vector(request_msg);
+      request_msg := pop(write_reply_queue);
+      msg_type := message_type(request_msg);
+      addr := pop_std_ulogic_vector(request_msg);
+      id := pop_std_ulogic_vector(request_msg);
+      resp := pop_std_ulogic_vector(request_msg);
 
-    check_axi_id(axi_master_handle.p_bus_handle, bid, id, "bid");
-    check_axi_resp(axi_master_handle.p_bus_handle, bresp, resp, "bresp");
+      check_axi_id(axi_master_handle.p_bus_handle, bid, id, "bid");
+      check_axi_resp(axi_master_handle.p_bus_handle, bresp, resp, "bresp");
 
-    delete(request_msg);
+      delete(request_msg);
+    end if;
   end process;
 
 end architecture;

vunit/vhdl/verification_components/test/tb_axi_master.vhd

@@ -277,12 +277,31 @@ begin
       wait until rising_edge(arvalid);
       areset_n <= '0' after 2ns;
       wait until rising_edge(clk);
-      check_equal(arvalid, '0', "ARVALID not 0 when ARESET_N low");
+      check_equal(arvalid, '0', "ARVALID 0 when ARESET_N low");
       wait until rising_edge(clk);
       info(tb_logger, "Release reset asyncron...");
       areset_n <= '1' after 0ps;
       wait until rising_edge(clk);
-      check_equal(arvalid, '0', "ARVALID not 0 after ARESET_N low");
+      check_equal(arvalid, '0', "ARVALID 0 after ARESET_N low");
+    elsif run("Test write asyncron reset") then
+      info(tb_logger, "Setup...");
+      burst := 1;
+      setup_and_set_random_data_write_memory(memory, burst, wdata'length, memory_data_queue);
+      info(tb_logger, "Reading...");
+      write_axi(net, axi_master_handle.p_bus_handle, x"00000000", pop(memory_data_queue), "001", x"25", axi_resp_okay);
+      info(tb_logger, "Sync on clk edge...");
+      wait until rising_edge(clk);
+      info(tb_logger, "Set reset asyncron...");
+      wait until rising_edge(awvalid);
+      areset_n <= '0' after 2ns;
+      wait until rising_edge(clk);
+      check_equal(arvalid, '0', "AWVALID 0 when ARESET_N low");
+      wait until rising_edge(clk);
+      info(tb_logger, "Release reset asyncron...");
+      areset_n <= '1' after 0ps;
+      wait until rising_edge(clk);
+      check_equal(awvalid, '0', "AWVALID 0 after ARESET_N low");
+      check_equal(wvalid, '0', "WVALID 0 after ARESET_N low");
     end if;
 
     wait for 100 ns;