add support for sync interface

Author: c-thaler

vunit/vhdl/verification_components/src/apb_master.vhd

@@ -71,6 +71,8 @@ begin
           wait until is_idle and queues_empty and rising_edge(clk);
         end if;
         handle_wait_until_idle(net, msg_type, request_msg);
+      elsif msg_type = wait_for_time_msg then
+        push(message_queue, request_msg);
       else
         unexpected_msg_type(msg_type);
       end if;
@@ -144,6 +146,11 @@ begin
         reply_msg := new_msg;
         push_std_ulogic_vector(reply_msg, prdata_i);
         reply(net, request_msg, reply_msg);
+
+      elsif msg_type = wait_for_time_msg then
+        handle_wait_for_time(net, msg_type, request_msg);
+        -- Re-align with the clock when a wait for time message was handled, because this breaks edge alignment.
+        wait until rising_edge(clk);
       end if;
 
       idle_bus <= true;

vunit/vhdl/verification_components/src/apb_master_pkg.vhd

@@ -12,6 +12,7 @@ use work.bus_master_pkg.all;
 use work.com_pkg.all;
 use work.com_types_pkg.all;
 use work.logger_pkg.all;
+use work.sync_pkg.all;
 use work.memory_pkg.memory_t;
 use work.memory_pkg.to_vc_interface;
 
@@ -49,9 +50,6 @@ package apb_master_pkg is
                       -- default byte enable is all bytes
                       constant byte_enable : std_logic_vector := "");
 
-  procedure wait_until_idle(signal net : inout network_t;
-                            bus_handle : apb_master_t);
-
   -- Non blocking: Read the bus returning a reference to the future reply
   procedure read_bus(signal net : inout network_t;
                      constant bus_handle : apb_master_t;
@@ -107,6 +105,14 @@ package apb_master_pkg is
     value        : std_logic;
     timeout      : delay_length := delay_length'high;
     msg    : string       := "");
+
+  procedure wait_until_idle(signal net : inout network_t;
+                            handle     :       apb_master_t;
+                            timeout    :       delay_length := max_timeout);
+
+  procedure wait_for_time(signal net : inout network_t;
+                            handle     :       apb_master_t;
+                            delay      :       delay_length);
 end package;
 
 package body apb_master_pkg is
@@ -168,12 +174,6 @@ package body apb_master_pkg is
     write_bus(net, bus_handle.p_bus_handle, address, data, byte_enable);
   end procedure;
 
-  procedure wait_until_idle(signal net : inout network_t;
-                            bus_handle : apb_master_t) is
-  begin
-    wait_until_idle(net, bus_handle.P_bus_handle);
-  end procedure;
-
   -- Blocking: read bus with immediate reply
   procedure read_bus(signal net : inout network_t;
                      constant bus_handle : apb_master_t;
@@ -252,4 +252,18 @@ package body apb_master_pkg is
   begin
     wait_until_read_bit_equals(net, bus_handle.p_bus_handle, addr, idx, value, timeout, msg);
   end procedure;
+
+  procedure wait_until_idle(signal net : inout network_t;
+                            handle     :       apb_master_t;
+                            timeout    :       delay_length := max_timeout) is
+  begin
+    wait_until_idle(net, handle.p_bus_handle.p_actor, timeout);
+  end procedure;
+
+  procedure wait_for_time(signal net : inout network_t;
+                          handle     :       apb_master_t;
+                          delay      :       delay_length) is
+  begin
+    wait_for_time(net, handle.p_bus_handle.p_actor, delay);
+  end procedure;
 end package body;

vunit/vhdl/verification_components/test/tb_apb_master.vhd

@@ -116,6 +116,16 @@ begin
       wait_until_idle(net, bus_handle);
       check_expected_was_written(memory);
 
+    elsif run("wait_between_writes") then
+      buf := allocate(memory => memory, num_bytes => 4, permissions => write_only);
+      set_expected_word(memory, base_address(buf), x"1234");
+      set_expected_word(memory, base_address(buf)+2, x"5678");
+      write_bus(net, bus_handle, base_address(buf), x"1234");
+      wait_for_time(net, bus_handle, 500 ns);
+      write_bus(net, bus_handle, base_address(buf)+2, x"5678");
+      wait_until_idle(net, bus_handle);
+      check_expected_was_written(memory);
+
     end if;
 
     wait for 100 ns;