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1 parent bfd7ee8 commit 91db1a3Copy full SHA for 91db1a3
examples/vhdl/array_axis_vcs/run.py
@@ -29,6 +29,6 @@
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VU.add_library("lib").add_source_files([SRC_PATH / "*.vhd", SRC_PATH / "**" / "*.vhd"])
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-# VU.set_sim_option('modelsim.init_files.after_load',['runall_addwave.do'])
+VU.set_sim_option("modelsim.init_file.gui", "runall_addwave.do")
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VU.main()
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