implement wait states

Author: c-thaler

vunit/vhdl/verification_components/src/apb_slave.vhd

@@ -8,6 +8,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library osvvm;
+use osvvm.RandomPkg.RandomPType;
+
 use work.memory_pkg.all;
 use work.apb_pkg.all;
 use work.logger_pkg.all;
@@ -45,6 +48,7 @@ begin
     end procedure;
 
     variable addr : integer;
+    variable rnd : RandomPType;
   begin
     drive_outputs_invalid;
     wait until rising_edge(clk);
@@ -56,6 +60,11 @@ begin
       wait until psel_i = '1' and rising_edge(clk);
       -- ACCESS state
 
+      while rnd.Uniform(0.0, 1.0) > bus_handle.ready_high_probability loop
+        pready_o <= '0';
+        wait until rising_edge(clk);
+      end loop;
+
       pready_o <= '1';
 
       addr := to_integer(unsigned(paddr_i));

vunit/vhdl/verification_components/test/tb_apb_master.vhd

@@ -43,14 +43,15 @@ architecture a of tb_apb_master is
                                                 address_length => paddr'length);
   constant memory : memory_t := new_memory;
   constant slave_handle : apb_slave_t := new_apb_slave(memory => memory,
-                                                       logger => get_logger("apb slave"));
+                                                       logger => get_logger("apb slave"),
+                                                       ready_high_probability => 0.5);
 
   signal start : boolean := false;
 begin
 
   main_stim : process
     variable buf : buffer_t;
-    variable data : std_logic_vector(prdata'range);
+    variable data, data2 : std_logic_vector(prdata'range);
     variable bus_ref1, bus_ref2 : bus_reference_t;
   begin
     show(get_logger("apb slave"), display_handler, debug);
@@ -95,6 +96,25 @@ begin
       wait_until_idle(net, bus_handle);
       check_expected_was_written(memory);
 
+    elsif run("many_reads") then
+      for i in 1 to 100 loop
+        buf := allocate(memory => memory, num_bytes => 2, permissions => read_only);
+        data := std_logic_vector(to_unsigned(i, BUS_DATA_WIDTH));
+        write_word(memory, base_address(buf), data);
+        read_bus(net, bus_handle, base_address(buf), data2);
+        check_equal(data2, data, "Check read data.");
+      end loop;
+
+    elsif run("many_writes") then
+      for i in 1 to 100 loop
+        buf := allocate(memory => memory, num_bytes => 2, permissions => write_only);
+        data := std_logic_vector(to_unsigned(i, BUS_DATA_WIDTH));
+        set_expected_word(memory, base_address(buf), data);
+        write_bus(net, bus_handle, base_address(buf), data);
+      end loop;
+      wait_until_idle(net, bus_handle);
+      check_expected_was_written(memory);
+
     end if;
 
     wait for 100 ns;