Add support for non-byte tdata widths in AXI stream VCs.

This is non-standard and must explicitly be enabled. The difference from
the standard implementation is with respect to the length of tkeep and
tstrb which is calculated as (tdata'length + 7) / 8 rather than tdata'length / 8 .

Author: LarsAsplund

docs/news.d/1127.breaking.rst

@@ -0,0 +1,13 @@
+The AXI stream standard requires tdata to be a multiple of 8 bits. VUnit VCs allowed non-standard widths but the tkeep and tstrb
+signals didn't cover the most significant bits beyond the last full byte. For example, if the tdata width was 12 bits, tkeep and tstrb
+were one bit corresponding to the least significant byte in tdata. The 4 most significant bits didn't have a corresponding tkeep
+bit.
+
+Starting in VUnit v5.0.0-dev2, the check features for AXI stream were updated such that comparison of the actual tdata value with the
+expected one, only considers bytes for which tkeep and tstrb are set. As a consequence, the upper bits of non-standard width tdata,
+for which there is no tkeep and tstrb bits, were not considered for comparison.
+
+The VCs have now been updated to extend tkeep and tstrb in these cases such that all bits in tdata are considered for comparison.
+Since this is a standard violation, non-standard widths must be enabled in the call to the VC constructor (the new function) by setting
+the allow_arbitrary_data_length parameter to true. Existing testbenches using non-standard widths will have to be updated.
+

vunit/vhdl/verification_components/run.py

@@ -134,7 +134,7 @@ def gen_avalon_master_tests(obj, *args):
 for id_length in [0, 8]:
     for dest_length in [0, 8]:
         for user_length in [0, 8]:
-            for data_length in [8, 16]:
+            for data_length in [0, 3, 8, 11, 16]:
                 for test in TB_AXI_STREAM.get_tests("*check"):
                     test.add_config(
                         name=f"id_l={id_length} dest_l={dest_length} user_l={user_length} data_l={data_length}",
@@ -150,7 +150,7 @@ def gen_avalon_master_tests(obj, *args):
 
 TB_AXI_STREAM_PROTOCOL_CHECKER = LIB.test_bench("tb_axi_stream_protocol_checker")
 
-for data_length in [0, 8, 32]:
+for data_length in [0, 3, 8, 11, 32]:
     for test in TB_AXI_STREAM_PROTOCOL_CHECKER.get_tests("*passing*tdata*"):
         test.add_config(name="data_length=%d" % data_length, generics=dict(data_length=data_length))
 

vunit/vhdl/verification_components/src/axi_stream_master.vhd

@@ -37,8 +37,8 @@ entity axi_stream_master is
     tready       : in  std_logic                                          := '1';
     tdata        : out std_logic_vector(data_length(master)-1 downto 0)   := (others => '0');
     tlast        : out std_logic                                          := '0';
-    tkeep        : out std_logic_vector(data_length(master)/8-1 downto 0) := (others => '1');
-    tstrb        : out std_logic_vector(data_length(master)/8-1 downto 0) := (others => '1');
+    tkeep        : out std_logic_vector(keep_strb_length(master)-1 downto 0) := (others => '1');
+    tstrb        : out std_logic_vector(keep_strb_length(master)-1 downto 0) := (others => '1');
     tid          : out std_logic_vector(id_length(master)-1 downto 0)     := (others => '0');
     tdest        : out std_logic_vector(dest_length(master)-1 downto 0)   := (others => '0');
     tuser        : out std_logic_vector(user_length(master)-1 downto 0)   := (others => '0')
@@ -55,8 +55,8 @@ architecture a of axi_stream_master is
 
 
   procedure drive_invalid_output(signal l_tdata : out std_logic_vector(data_length(master)-1 downto 0);
-                                 signal l_tkeep : out std_logic_vector(data_length(master)/8-1 downto 0);
-                                 signal l_tstrb : out std_logic_vector(data_length(master)/8-1 downto 0);
+                                 signal l_tkeep : out std_logic_vector(keep_strb_length(master)-1 downto 0);
+                                 signal l_tstrb : out std_logic_vector(keep_strb_length(master)-1 downto 0);
                                  signal l_tid   : out std_logic_vector(id_length(master)-1 downto 0);
                                  signal l_tdest : out std_logic_vector(dest_length(master)-1 downto 0);
                                  signal l_tuser : out std_logic_vector(user_length(master)-1 downto 0))

vunit/vhdl/verification_components/src/axi_stream_monitor.vhd

@@ -24,8 +24,8 @@ entity axi_stream_monitor is
     tready : in std_logic := '1';
     tdata  : in std_logic_vector(data_length(monitor) - 1 downto 0);
     tlast  : in std_logic := '1';
-    tkeep  : in std_logic_vector(data_length(monitor)/8-1 downto 0) := (others => '1');
-    tstrb  : in std_logic_vector(data_length(monitor)/8-1 downto 0) := (others => 'U');
+    tkeep  : in std_logic_vector(keep_strb_length(monitor)-1 downto 0) := (others => '1');
+    tstrb  : in std_logic_vector(keep_strb_length(monitor)-1 downto 0) := (others => 'U');
     tid    : in std_logic_vector(id_length(monitor)-1 downto 0) := (others => '0');
     tdest  : in std_logic_vector(dest_length(monitor)-1 downto 0) := (others => '0');
     tuser  : in std_logic_vector(user_length(monitor)-1 downto 0) := (others => '0')