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Anton Schulte
committed
Fixed for python 3.7
1 parent a73d9e7 commit fb7df06

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17 files changed

+71
-73
lines changed

17 files changed

+71
-73
lines changed

tests/common.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ def set_env(**environ):
7272
>>> "PLUGINS_DIR" in os.environ
7373
False
7474
75-
:type environ: dict[str, unicode]
75+
:type environ: Dict[str, unicode]
7676
:param environ: Environment variables to set
7777
"""
7878
old_environ = dict(os.environ)

vunit/com/codec_vhdl_package.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ def _create_enumeration_of_all_msg_types(self):
148148

149149
msg_type_enumeration_types = []
150150
for record in self.record_types:
151-
if record.elements[0].identifier_list[0] == "msg_type":
151+
if record.elements[0].identifier_List[0] == "msg_type":
152152
msg_type_enumeration_types.append(record.elements[0].subtype_indication.code)
153153

154154
msg_type_enumeration_literals = []
@@ -276,7 +276,7 @@ def _get_records_with_an_initial_msg_type_element(self):
276276

277277
msg_type_record_types = []
278278
for record in self.record_types:
279-
if record.elements[0].identifier_list[0] == "msg_type":
279+
if record.elements[0].identifier_List[0] == "msg_type":
280280
msg_type_record_types.append(record)
281281

282282
return msg_type_record_types

vunit/configuration.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
import inspect
1313
from pathlib import Path
1414
from copy import copy
15-
from typing import Any, Callable, OrderedDict, Union
15+
from typing import Any, Callable, List, OrderedDict, Union
1616
from vunit.sim_if.factory import SIMULATOR_FACTORY
1717

1818

@@ -129,7 +129,7 @@ def set_generic(self, name: str, value: Any) -> None:
129129
else:
130130
self.generics[name] = value
131131

132-
def set_sim_option(self, name: str, value: Union[str, list[str], bool]):
132+
def set_sim_option(self, name: str, value: Union[str, List[str], bool]):
133133
"""
134134
Set sim option
135135
"""
@@ -196,7 +196,7 @@ class ConfigurationVisitor(object):
196196
def _check_enabled(self):
197197
pass
198198

199-
def get_configuration_dicts(self) -> list[OrderedDict[Any, Configuration]]:
199+
def get_configuration_dicts(self) -> List[OrderedDict[Any, Configuration]]:
200200
raise NotImplementedError
201201

202202
def set_attribute(self, name: str, value: Any):
@@ -226,7 +226,7 @@ def set_vhdl_configuration_name(self, value: str):
226226
for config in configs.values():
227227
config.set_vhdl_configuration_name(value)
228228

229-
def set_sim_option(self, name: str, value: Union[str, list[str], bool], overwrite=True) -> None:
229+
def set_sim_option(self, name: str, value: Union[str, List[str], bool], overwrite=True) -> None:
230230
"""
231231
Set sim option
232232

vunit/library.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
"""
1212

1313
import logging
14-
from typing import cast, TYPE_CHECKING
14+
from typing import List, cast, TYPE_CHECKING
1515
from vunit.design_unit import Entity, VHDLDesignUnit
1616
from vunit.vhdl_standard import VHDLStandard
1717

@@ -109,7 +109,7 @@ def _check_duplication(self, dictionary, design_unit):
109109
if design_unit.name in dictionary:
110110
self._warning_on_duplication(design_unit, dictionary[design_unit.name].source_file.name)
111111

112-
def add_vhdl_design_units(self, design_units: list[VHDLDesignUnit]):
112+
def add_vhdl_design_units(self, design_units: List[VHDLDesignUnit]):
113113
"""
114114
Add VHDL design units to the library
115115
"""

vunit/project.py

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,9 @@
99
"""
1010
Functionality to represent and operate on a HDL code project
1111
"""
12-
from typing import Optional, Union
12+
from typing import List, Optional, Union, OrderedDict
1313
from pathlib import Path
1414
import logging
15-
from collections import OrderedDict
1615
from vunit.hashing import hash_string
1716
from vunit.dependency_graph import DependencyGraph, CircularDependencyException
1817
from vunit.vhdl_parser import VHDLParser
@@ -48,7 +47,7 @@ def __init__(self, depend_on_package_body=False, database=None):
4847
self._libraries: OrderedDict[str, Library] = OrderedDict()
4948
# Mapping between library lower case name and real library name
5049
self._lower_library_names_dict = {}
51-
self._source_files_in_order: list[SourceFile] = []
50+
self._source_files_in_order: List[SourceFile] = []
5251
self._manual_dependencies = []
5352
self._depend_on_package_body = depend_on_package_body
5453
self._builtin_libraries = set(["ieee", "std"])
@@ -517,7 +516,7 @@ def _get_files_to_recompile(self, files, dependency_graph, incremental):
517516

518517
def get_dependencies_in_compile_order(
519518
self, target_files=None, implementation_dependencies=False
520-
) -> list[SourceFile]:
519+
) -> List[SourceFile]:
521520
"""
522521
Get a list of dependencies of target files including the
523522
target files.
@@ -593,7 +592,7 @@ def comparison_key(source_file):
593592

594593
return sorted(files, key=comparison_key)
595594

596-
def get_source_files_in_order(self) -> list[SourceFile]:
595+
def get_source_files_in_order(self) -> List[SourceFile]:
597596
"""
598597
Get a list of source files in the order they were added to the project
599598
"""

vunit/sim_if/__init__.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
from ..exceptions import CompileError
1919
from ..color_printer import NO_COLOR_PRINTER
2020

21-
OptionType = Union[str, list[str], bool]
21+
OptionType = Union[str, List[str], bool]
2222

2323

2424
class Option(object):

vunit/sim_if/factory.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
"""
1010

1111
import os
12-
from typing import Union
12+
from typing import Dict, List, Union
1313
from .activehdl import ActiveHDLInterface
1414
from .ghdl import GHDLInterface
1515
from .incisive import IncisiveInterface
@@ -38,7 +38,7 @@ def supported_simulators():
3838
NVCInterface,
3939
]
4040

41-
def _extract_compile_options(self) -> dict[str, Option]:
41+
def _extract_compile_options(self) -> Dict[str, Option]:
4242
"""
4343
Return all supported compile options
4444
"""
@@ -52,7 +52,7 @@ def _extract_compile_options(self) -> dict[str, Option]:
5252
result[opt.name] = opt
5353
return result
5454

55-
def _extract_sim_options(self) -> dict[str, Option]:
55+
def _extract_sim_options(self) -> Dict[str, Option]:
5656
"""
5757
Return all supported sim options
5858
"""
@@ -76,7 +76,7 @@ def _extract_sim_options(self) -> dict[str, Option]:
7676

7777
return result
7878

79-
def check_sim_option(self, name: str, value: Union[str, list[str], bool]):
79+
def check_sim_option(self, name: str, value: Union[str, List[str], bool]):
8080
"""
8181
Check that sim_option has legal name and value
8282
"""
@@ -95,7 +95,7 @@ def check_compile_option_name(self, name):
9595
if name not in known_options:
9696
raise ValueError(f"Unknown compile_option {name!r}, expected one of {known_options!r}")
9797

98-
def check_compile_option(self, name: str, value: Union[str, list[str], bool]) -> None:
98+
def check_compile_option(self, name: str, value: Union[str, List[str], bool]) -> None:
9999
"""
100100
Check that the compile option is valid
101101
"""

vunit/source_file.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
Functionality to represent and operate on VHDL and Verilog source files
99
"""
1010
from pathlib import Path
11-
from typing import Literal, Union
11+
from typing import Dict, Union
1212
import logging
1313
from copy import copy
1414
import traceback
@@ -36,7 +36,7 @@ def __init__(self, name, library, file_type):
3636
self.file_type = file_type
3737
self.design_units = []
3838
self._content_hash = None
39-
self._compile_options: dict[str, OptionType] = {}
39+
self._compile_options: Dict[str, OptionType] = {}
4040

4141
# The file name before preprocessing
4242
self.original_name = name
@@ -351,7 +351,7 @@ def add_to_library(self, library):
351351
FILE_TYPES = ("vhdl",) + VERILOG_FILE_TYPES
352352

353353

354-
def file_type_of(file_name: Union[str, Path]) -> Literal["vhdl", "verilog", "systemverilog"]:
354+
def file_type_of(file_name: Union[str, Path]) -> str:
355355
"""
356356
Return the file type of file_name based on the file ending
357357
"""

vunit/test/bench.py

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,7 @@
1313
import re
1414
import bisect
1515
import collections
16-
from collections import OrderedDict
17-
from typing import Any, Iterable, Union
16+
from typing import Any, Iterable, List, Union, OrderedDict
1817
from ..ostools import file_exists
1918
from ..cached import cached
2019
from ..vhdl_parser import remove_comments as remove_vhdl_comments
@@ -143,7 +142,7 @@ def get_test_case(self, name):
143142
return test_case
144143
raise KeyError(name)
145144

146-
def get_configuration_dicts(self) -> list[OrderedDict[str, Configuration]]: # pylint: disable=arguments-differ
145+
def get_configuration_dicts(self) -> "List[OrderedDict[str, Configuration]]": # pylint: disable=arguments-differ
147146
"""
148147
Get all configurations within the test bench
149148
@@ -359,7 +358,7 @@ def _check_enabled(self):
359358
if not self._enable_configuration:
360359
raise RuntimeError("Individual test configuration is not possible with run_all_in_same_sim")
361360

362-
def get_configuration_dicts(self) -> list[OrderedDict[Any, Configuration]]: # pylint: disable=arguments-differ
361+
def get_configuration_dicts(self) -> List[OrderedDict[Any, Configuration]]: # pylint: disable=arguments-differ
363362
"""
364363
Get all configurations of this test
365364
"""

vunit/test/bench_list.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010

1111
import re
1212
import logging
13-
from collections import OrderedDict
13+
from typing import List, OrderedDict
1414

1515
from vunit.source_file import SourceFile
1616
from .list import TestList
@@ -49,10 +49,10 @@ def _add_test_bench(self, test_bench: TestBench) -> None:
4949
def get_test_bench(self, library_name, name) -> TestBench:
5050
return self._libraries[library_name][name]
5151

52-
def get_test_benches_in_library(self, library_name: str) -> list[TestBench]:
52+
def get_test_benches_in_library(self, library_name: str) -> List[TestBench]:
5353
return list(self._libraries.get(library_name, {}).values())
5454

55-
def get_test_benches(self) -> list[TestBench]:
55+
def get_test_benches(self) -> List[TestBench]:
5656
"""
5757
Get all test benches
5858
"""

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